| /linux/drivers/infiniband/hw/mlx5/ |
| H A D | qpc.c | 13 struct mlx5_core_dct *dct);
93 struct mlx5_core_dct *dct; in dct_event_notifier() local
97 qpn = be32_to_cpu(eqe->data.dct.dctn) & 0xFFFFFF; in dct_event_notifier()
99 dct = xa_load(&dev->qp_table.dct_xa, qpn); in dct_event_notifier()
100 if (dct) in dct_event_notifier()
101 complete(&dct->drained); in dct_event_notifier()
196 struct mlx5_core_dct *dct) in _mlx5_core_destroy_dct() argument
199 struct mlx5_core_qp *qp = &dct->mqp; in _mlx5_core_destroy_dct()
207 int mlx5_core_create_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct, in mlx5_core_create_dct() argument
210 struct mlx5_core_qp *qp = &dct->mqp; in mlx5_core_create_dct()
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| H A D | qp.h | 31 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct);
34 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
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| H A D | qp.c | 2739 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); in create_dct()
2740 if (!qp->dct.in) in create_dct()
2743 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); in create_dct()
2744 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); in create_dct()
2767 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) in check_qp_type()
3182 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); in mlx5_ib_destroy_dct()
3184 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); in mlx5_ib_destroy_dct()
3189 kfree(mqp->dct.in); in mlx5_ib_destroy_dct()
4480 /* mlx5_ib_modify_dct: modify a DCT QP
4504 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); in mlx5_ib_modify_dct()
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| H A D | restrack.c | 173 ret = nla_put_string(msg, RDMA_NLDEV_ATTR_RES_SUBTYPE, "DCT"); in fill_res_qp_entry()
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | hantro_g1_vp8_dec.c | 18 /* DCT partition base address regs */
71 /* DCT partition start bits regs */
207 * set control partition and DCT partition regs
217 * | tag 3B | extra 7B | hdr | mb_data | DCT sz | DCT part0 | ... | DCT partn |
223 * DCT size part
228 * 3. number of DCT parts is 1, 2, 4 or 8
285 * Calculate DCT partition info in cfg_parts()
286 * @dct_size_part_size: Containing sizes of DCT part, every DCT part in cfg_parts()
288 * DCT part in cfg_parts()
289 * @dct_part_offset: bytes offset of DCT parts from src_dma base addr in cfg_parts()
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| H A D | rockchip_vpu2_hw_vp8_dec.c | 387 * Calculate DCT partition info in cfg_parts()
388 * @dct_size_part_size: Containing sizes of DCT part, every DCT part in cfg_parts()
390 * DCT part in cfg_parts()
391 * @dct_part_offset: bytes offset of DCT parts from src_dma base addr in cfg_parts()
392 * @dct_part_total_len: total size of all DCT parts in cfg_parts()
401 /* Number of DCT partitions */ in cfg_parts()
405 /* DCT partition length */ in cfg_parts()
408 /* DCT partitions base address */ in cfg_parts()
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| /linux/drivers/edac/ |
| H A D | amd64_edac.c | 100 * Select DCT to which PCI cfg accesses are routed
102 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
108 reg |= dct; in f15h_select_dct()
114 * Depending on the family, F2 DCT reads need special handling:
116 * K8: has a single DCT only and no address offsets >= 0x100
118 * F10h: each DCT has its own set of regs
122 * F16h: has only 1 DCT
124 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
126 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
131 if (dct || offset >= 0x100) in amd64_read_dct_pci_cfg()
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| H A D | amd64_edac.h | 166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) argument
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) argument
292 /* A DCT chip selects collection */
348 /* one for each DCT/UMC */
463 int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
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| /linux/drivers/accel/ivpu/ |
| H A D | ivpu_pm.c | 414 ivpu_err_ratelimited(vdev, "Filed to enable DCT: %d\n", ret); in ivpu_pm_dct_enable()
420 ivpu_dbg(vdev, PM, "DCT set to %u%% (D0: %uus, D0i2: %uus)\n", in ivpu_pm_dct_enable()
431 ivpu_err_ratelimited(vdev, "Filed to disable DCT: %d\n", ret); in ivpu_pm_dct_disable()
437 ivpu_dbg(vdev, PM, "DCT disabled\n"); in ivpu_pm_dct_disable()
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| H A D | vpu_jsm_api.h | 317 /* Control command: Enable survivability/DCT mode */
319 /* Control command: Disable survivability/DCT mode */
416 /* Response to control command: Enable survivability/DCT mode */
418 /* Response to control command: Disable survivability/DCT mode */
1222 * Default values for DCT active/inactive times are 5.3ms and 30ms respectively,
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| H A D | vpu_boot_api.h | 377 /* Microsecond value for DCT active cycle */
379 /* Microsecond value for DCT inactive cycle */
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| H A D | ivpu_debugfs.c | 457 debugfs_create_file("dct", 0644, debugfs_root, vdev, &ivpu_dct_fops); in ivpu_debugfs_init()
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| /linux/drivers/media/v4l2-core/ |
| H A D | v4l2-jpeg.c | 291 * Baseline DCT only supports 8-bit precision. in jpeg_parse_frame_header()
292 * Extended sequential DCT also supports 12-bit precision. in jpeg_parse_frame_header()
428 /* Lq = 2 + n * 65 (for baseline DCT), n >= 1 */ in jpeg_parse_quantization_tables()
445 * sequential DCT with 12-bit sample precision also supports in jpeg_parse_quantization_tables()
501 /* only two Huffman tables for baseline DCT */ in jpeg_parse_huffman_tables()
632 /* baseline DCT, extended sequential DCT */ in v4l2_jpeg_parse_header()
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| /linux/drivers/media/pci/bt8xx/ |
| H A D | dst.c | 463 } else if (!strncmp(state->fw_name, "DCT-CI", 6)) { in dst_set_symbolrate()
495 else if (!strncmp(state->fw_name, "DCT-CI", 6)) in dst_set_modulation()
644 .fw_name = "DCT-CI"
651 .fw_name = "DCT-CI"
658 .fw_name = "DCT-CI"
720 VP-2030 DCT-CI, Samsung, TS=204
721 VP-2021 DCT-CI, Unknown, TS=204
722 VP-2031 DCT-CI, Philips, TS=188
723 VP-2040 DCT-CI, Philips, TS=188, with CA daughter board
724 VP-2040 DCT-CI, Philips, TS=204, without CA daughter board
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| /linux/drivers/i3c/master/mipi-i3c-hci/ |
| H A D | dct.h | 7 * Common DCT related stuff
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| H A D | dct_v1.c | 14 #include "dct.h"
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| H A D | cmd_v1.c | 16 #include "dct.h"
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| H A D | core.c | 184 /* located here rather than dct.c because needed bits are in core reg space */
676 dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n", in i3c_hci_init()
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | nxp,imx8-jpeg.yaml | 15 and Extended Sequential DCT modes.
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| /linux/Documentation/admin-guide/media/ |
| H A D | ivtv-cardlist.rst | 86 - Digital Cowboy DCT-MTVP1
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | ext-ctrls-jpeg.rst | 11 progressive baseline DCT compression process with Huffman entropy
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| /linux/include/media/ |
| H A D | v4l2-jpeg.h | 39 /* Array size for 8x8 block of samples or DCT coefficient */
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| /linux/drivers/soc/fsl/dpio/ |
| H A D | qbman-portal.c | 1065 * @dct: the dequeue command type
1068 enum qbman_pull_type_e dct) in qbman_pull_desc_set_wq() argument
1070 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_wq()
1080 * @dct: the dequeue command type
1083 enum qbman_pull_type_e dct) in qbman_pull_desc_set_channel() argument
1085 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_channel()
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| H A D | qbman-portal.h | 215 enum qbman_pull_type_e dct);
217 enum qbman_pull_type_e dct);
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| /linux/drivers/media/pci/ivtv/ |
| H A D | ivtv-cards.h | 32 #define IVTV_CARD_DCTMTVP1 17 /* DIGITAL COWBOY DCT-MTVP1 */
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