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/linux/include/video/
H A Dmipi_display.h4 * Display Working Group standards: DSI, DCS, DBI, DPI
78 /* MIPI DCS commands */
111 MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
128 MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
129 MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */
130 MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */
131 MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */
132 MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */
133 MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */
134 MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-samsung-s6e63m0-dsi.c27 dev_err(dev, "could not read DCS CMD %02x\n", cmd); in s6e63m0_dsi_dcs_read()
47 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
49 /* Pick out and skip past the DCS command */ in s6e63m0_dsi_dcs_write()
61 dev_err(dev, "error sending DCS command seq cmd %02x\n", cmd); in s6e63m0_dsi_dcs_write()
H A Dpanel-sharp-lq101r1sx01.c60 dev_err(&dsi->dev, "failed to send DCS nop: %zd\n", err); in sharp_panel_write()
166 * The MIPI DCS specification mandates this delay only between the in sharp_panel_prepare()
H A Dpanel-novatek-nt36672a.c125 dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret); in nt36672a_panel_unprepare()
131 /* 120ms delay required here as per DCS spec */ in nt36672a_panel_unprepare()
184 dev_err(panel->dev, "failed to send DCS Init 1st Code: %d\n", err); in nt36672a_panel_prepare()
208 dev_err(panel->dev, "failed to send DCS Init 2nd Code: %d\n", err); in nt36672a_panel_prepare()
H A Dpanel-truly-nt35597.c336 /* 120ms delay required here as per DCS spec */ in truly_nt35597_unprepare()
387 /* Per DSI spec wait 120ms after sending exit sleep DCS command */ in truly_nt35597_prepare()
396 /* Per DSI spec wait 120ms after sending set_display_on DCS command */ in truly_nt35597_prepare()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h725 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
726 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
727 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz
729 …uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXO…
731 …t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
732 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
734 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
736 …f time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
1085 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
1086 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
[all …]
H A Dsmu13_driver_if_v13_0_0.h1066 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1096 // GFX DCS
1098 …uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXO…
1101 …t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1102 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1104 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1106 …of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
H A Dsmu13_driver_if_v13_0_7.h1075 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1100 // GFX DCS
1102 …uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXO…
1105 …t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1106 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1108 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1110 …of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
H A Dsmu14_driver_if_v14_0.h1162 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1195 // GFX DCS
1198 …6_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1199 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1201 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1203 …of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
/linux/drivers/video/fbdev/omap/
H A DKconfig34 bool "MIPI DBI-C/DCS compatible LCD support"
38 the Mobile Industry Processor Interface DBI-C/DCS
H A Dlcd_mipid.c3 * LCD driver for MIPI DBI-C / DCS compatible LCDs
/linux/include/drm/
H A Ddrm_mipi_dbi.h210 * mipi_dbi_command - MIPI DCS command with optional parameter(s)
215 * Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916-samsung-rossa-common.dtsi27 /* On rossa backlight is controlled with MIPI DCS commands */
/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-mipi-dbi-spi.yaml56 The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR
/linux/drivers/nfc/pn533/
H A Dpn533.h29 #define PN533_STD_FRAME_TAIL_LEN 2 /* data[len] DCS, data[len + 1] postamble*/
/linux/sound/soc/codecs/
H A Dwm8903.c353 pr_warn("DCS mode %d delay not set\n", dcs_mode); in wm8903_seq_notifier()
914 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
1060 { "HPL_DCS", NULL, "DCS Master" },
1061 { "HPR_DCS", NULL, "DCS Master" },
1062 { "LINEOUTL_DCS", NULL, "DCS Master" },
1063 { "LINEOUTR_DCS", NULL, "DCS Master" },
/linux/arch/x86/math-emu/
H A DREADME406 Nick Holloway, alfie@dcs.warwick.ac.uk
407 Hermano Moura, moura@dcs.gla.ac.uk
/linux/fs/ufs/
H A Dialloc.c19 * Stephen Tweedie (sct@dcs.ed.ac.uk), 1993
/linux/drivers/staging/fbtft/
H A Dfb_st7789v.c52 * Furthermore, commands that are compliant with the MIPI DCS have been left
/linux/drivers/gpu/drm/tiny/
H A Dpanel-mipi-dbi.c297 * width and height don't exceed the 16-bit value specified by MIPI DCS. in panel_mipi_dbi_get_mode()
/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c779 * able to send DCS commands anymore, which would prevent any in sun6i_dsi_encoder_enable()
780 * panel to send any DCS command as part as their enable in sun6i_dsi_encoder_enable()
/linux/drivers/video/fbdev/
H A Dleo.c154 u32 dcs; /* SS1 only */ member
/linux/fs/btrfs/
H A Dblock-group.c3202 int dcs = BTRFS_DC_ERROR; in cache_save_setup() local
3270 dcs = BTRFS_DC_SETUP; in cache_save_setup()
3294 dcs = BTRFS_DC_WRITTEN; in cache_save_setup()
3339 dcs = BTRFS_DC_SETUP; in cache_save_setup()
3349 if (!ret && dcs == BTRFS_DC_SETUP) in cache_save_setup()
3351 block_group->disk_cache_state = dcs; in cache_save_setup()
/linux/drivers/gpu/drm/tegra/
H A Ddsi.c525 /* enable DCS commands for command mode */ in tegra_dsi_configure()
577 /* 1 byte (DCS command) + pixel data */ in tegra_dsi_configure()
/linux/fs/ext2/
H A Dialloc.c11 * Stephen Tweedie (sct@dcs.ed.ac.uk), 1993

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