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/linux/include/video/
H A Dmipi_display.h4 * Display Working Group standards: DSI, DCS, DBI, DPI
78 /* MIPI DCS commands */
111 MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
128 MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
129 MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */
130 MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */
131 MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */
132 MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */
133 MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */
134 MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-samsung-s6e63m0-dsi.c26 dev_err(dev, "could not read DCS CMD %02x\n", cmd); in s6e63m0_dsi_dcs_read()
46 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
48 /* Pick out and skip past the DCS command */ in s6e63m0_dsi_dcs_write()
60 dev_err(dev, "error sending DCS command seq cmd %02x\n", cmd); in s6e63m0_dsi_dcs_write()
H A Dpanel-sharp-lq101r1sx01.c60 dev_err(&dsi->dev, "failed to send DCS nop: %zd\n", err); in sharp_panel_write()
166 * The MIPI DCS specification mandates this delay only between the in sharp_panel_prepare()
H A Dpanel-visionox-rm69299.c201 /* 120ms delay required here as per DCS spec */ in visionox_rm69299_unprepare()
226 /* Per DSI spec wait 120ms after sending exit sleep DCS command */ in visionox_rm69299_prepare()
231 /* Per DSI spec wait 120ms after sending set_display_on DCS command */ in visionox_rm69299_prepare()
H A Dpanel-raydium-rm68200.c109 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err); in rm68200_dcs_write_buf()
119 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err); in rm68200_dcs_write_cmd()
H A Dpanel-boe-himax8279d.c145 dev_err(panel->dev, "failed to send DCS Init Code: %d\n", err); in boe_panel_prepare()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h725 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
726 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
727 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz
729 …uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXO…
731 …t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
732 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
734 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
736 …f time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
1085 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
1086 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
[all …]
H A Dsmu13_driver_if_v13_0_0.h1066 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1096 // GFX DCS
1098 …uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXO…
1101 …t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1102 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1104 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1106 …of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
H A Dsmu13_driver_if_v13_0_7.h1075 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1100 // GFX DCS
1102 …uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXO…
1105 …t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1106 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1108 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1110 …of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
H A Dsmu14_driver_if_v14_0.h1162 uint16_t GfxclkThrottleClock; //Used primarily in DCS
1195 // GFX DCS
1198 …6_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1199 …OffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1201 …inCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1203 …of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
/linux/drivers/video/fbdev/omap/
H A DKconfig34 bool "MIPI DBI-C/DCS compatible LCD support"
38 the Mobile Industry Processor Interface DBI-C/DCS
H A Dlcd_mipid.c3 * LCD driver for MIPI DBI-C / DCS compatible LCDs
/linux/drivers/dma/
H A Ddma-jz4780.c681 u32 dcs; in jz4780_dma_chan_irq() local
686 dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS); in jz4780_dma_chan_irq()
689 if (dcs & JZ_DMA_DCS_AR) { in jz4780_dma_chan_irq()
691 "address error (DCS=0x%x)\n", dcs); in jz4780_dma_chan_irq()
694 if (dcs & JZ_DMA_DCS_HLT) { in jz4780_dma_chan_irq()
696 "channel halt (DCS=0x%x)\n", dcs); in jz4780_dma_chan_irq()
700 jzchan->desc->status = dcs; in jz4780_dma_chan_irq()
702 if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) { in jz4780_dma_chan_irq()
707 } else if (dcs & JZ_DMA_DCS_TT) { in jz4780_dma_chan_irq()
/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-mipi-dbi-spi.yaml56 The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR
/linux/drivers/nfc/pn533/
H A Dpn533.h31 #define PN533_STD_FRAME_TAIL_LEN 2 /* data[len] DCS, data[len + 1] postamble*/
/linux/sound/soc/codecs/
H A Dwm8903.c354 pr_warn("DCS mode %d delay not set\n", dcs_mode); in wm8903_seq_notifier()
913 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
1059 { "HPL_DCS", NULL, "DCS Master" },
1060 { "HPR_DCS", NULL, "DCS Master" },
1061 { "LINEOUTL_DCS", NULL, "DCS Master" },
1062 { "LINEOUTR_DCS", NULL, "DCS Master" },
/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c861 /* Always insert DCS command */ in dsi_ctrl_enable()
1385 *data = buf[1]; /* strip out dcs type */ in dsi_short_read1_resp()
1402 data[0] = buf[1]; /* strip out dcs type */ in dsi_short_read2_resp()
1414 /* strip out 4 byte dcs header */ in dsi_long_read_resp()
2295 * since rx fifo is 16 bytes, dcs header is kept at first loop, in msm_dsi_host_cmd_rx()
2296 * after that dcs header lost during shift into registers in msm_dsi_host_cmd_rx()
/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-controller-main.yaml124 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
/linux/drivers/staging/fbtft/
H A Dfb_st7789v.c52 * Furthermore, commands that are compliant with the MIPI DCS have been left
/linux/drivers/gpu/drm/sti/
H A Dsti_vtg.c262 /* Set hsync and vsync position for HD DCS */ in vtg_set_mode()
/linux/drivers/video/fbdev/
H A Dleo.c154 u32 dcs; /* SS1 only */ member
/linux/drivers/net/wireless/ath/ath12k/
H A Dwmi.c8772 "DCS incumbent signal interference subtlv 0x%x invalid len %u\n", in ath12k_wmi_incumbent_signal_interference_subtlv_parser()
8793 ath12k_warn(ab, "Received invalid tag 0x%x for WMI DCS interference in subtlvs\n", in ath12k_wmi_incumbent_signal_interference_subtlv_parser()
8817 ath12k_warn(ab, "Received invalid tag 0x%x for WMI DCS interference event\n", in ath12k_wmi_dcs_interference_event_parser()
8834 "DCS interference event received with wrong chan width bmap 0x%x for 20 MHz", in ath12k_wmi_validate_interference_info()
8843 "DCS interference event received with wrong chan width bmap 0x%x for 40 MHz", in ath12k_wmi_validate_interference_info()
8853 "DCS interference event received with wrong chan width bmap 0x%x for 80 MHz", in ath12k_wmi_validate_interference_info()
8864 "DCS interference event received with wrong chan width bmap 0x%x for 160 MHz", in ath12k_wmi_validate_interference_info()
8876 "DCS interference event received with wrong chan width bmap 0x%x for 320 MHz", in ath12k_wmi_validate_interference_info()
8883 "DCS interference event received with unknown channel width %u", in ath12k_wmi_validate_interference_info()
8976 ath12k_warn(ab, "pdev does not support 6 GHz, dropping DCS interference event\n"); in ath12k_wmi_process_incumbent_signal_interference_evt()
[all …]
/linux/fs/btrfs/
H A Dblock-group.c3384 int dcs = BTRFS_DC_ERROR; in cache_save_setup() local
3457 dcs = BTRFS_DC_SETUP; in cache_save_setup()
3481 dcs = BTRFS_DC_WRITTEN; in cache_save_setup()
3524 dcs = BTRFS_DC_SETUP; in cache_save_setup()
3534 if (!ret && dcs == BTRFS_DC_SETUP) in cache_save_setup()
3536 block_group->disk_cache_state = dcs; in cache_save_setup()
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h1036 * Four fixed gamma curves are defined in section DCS spec.
1194 /* DCS Interface Pixel Formats */
/linux/drivers/infiniband/hw/mthca/
H A Dmthca_main.c919 dev_err(&pdev->dev, "Missing DCS, aborting.\n"); in __mthca_init_one()

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