Home
last modified time | relevance | path

Searched +full:dc +full:- +full:dc (Results 1 – 25 of 903) sorted by relevance

12345678910>>...37

/linux/drivers/dma/
H A Dtxx9dmac.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
[all …]
/linux/drivers/tty/
H A Dnozomi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
132 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
133 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
157 CTRL_ERROR = -1,
167 PORT_ERROR = -1,
176 * else A-channels must always be used.
246 * else A-channels must always be used.
[all …]
/linux/drivers/md/
H A Ddm-delay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2007 Red Hat GmbH
19 #include <linux/device-mapper.h>
59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
79 n = bio->bi_next; in flush_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c29 #include "dc.h"
93 dc->ctx
96 dc->ctx->logger
98 static const char DC_BUILD_ID[] = "production-build";
103 * DC is the OS-agnostic component of the amdgpu DC driver.
105 * DC maintains and validates a set of structs representing the state of the
108 * Main DC HW structs:
110 * struct dc - The central struct. One per driver. Created on driver load,
113 * struct dc_context - One per driver.
114 * Used as a backpointer by most other structs in dc.
[all …]
H A Ddc_stream.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
28 #include "dc.h"
37 #define DC_LOGGER dc->ctx->logger
57 if (sink->sink_signal == SIGNAL_TYPE_NONE) in update_stream_signal()
58 stream->signal = stream->link->connector_signal; in update_stream_signal()
60 stream->signal = sink->sink_signal; in update_stream_signal()
62 if (dc_is_dvi_signal(stream->signal)) { in update_stream_signal()
63 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
64 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && in update_stream_signal()
65 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) in update_stream_signal()
[all …]
H A Ddc_vm_helper.c27 #include "dc.h"
31 struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx]; in vm_helper_mark_vmid_used()
37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
45 /* Pre-init system aperture start/end for all HUBP instances (if not gating?) in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
51 dc_z10_save_init(dc); in dc_setup_system_context()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile24 # Makefile for the 'utils' sub-component of DAL.
42 ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
43 frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
47 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
48 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
53 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1 // SPDX-License-Identifier: MIT
47 hws->ctx
49 hws->regs->reg
51 dc->ctx->logger
56 hws->shifts->field_name, hws->masks->field_name
58 void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
60 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
62 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
33 #include "dc.h"
44 stats->frames = 0; in tegra_dc_stats_reset()
45 stats->vblank = 0; in tegra_dc_stats_reset()
46 stats->underflow = 0; in tegra_dc_stats_reset()
47 stats->overflow = 0; in tegra_dc_stats_reset()
51 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
55 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
8 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
85 struct esas2r_sas_nvram *nvr = a->nvram; in esas2r_disc_initialize()
89 clear_bit(AF_DISC_IN_PROG, &a->flags); in esas2r_disc_initialize()
90 clear_bit(AF2_DEV_SCAN, &a->flags2); in esas2r_disc_initialize()
91 clear_bit(AF2_DEV_CNT_OK, &a->flags2); in esas2r_disc_initialize()
93 a->disc_start_time = jiffies_to_msecs(jiffies); in esas2r_disc_initialize()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c27 #include "dc.h"
76 * For eDP, after power-up/power/down,
86 hws->ctx
89 dc_ctx->logger
94 hws->regs->reg
98 hws->shifts->field_name, hws->masks->field_name
106 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
109 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
112 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
115 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_stream.h2 * Copyright 2012-14 Advanced Micro Devices, Inc.
105 /* source MPCC instance. for use by internally by dc */
167 * When force_odm_combine_segments is non zero, allow dc to
296 /* Output from DC when stream state is committed or altered
297 * DC may only access these values during:
399 bool dc_update_planes_and_stream(struct dc *dc,
409 struct dc *dc,
441 void dc_commit_updates_for_stream(struct dc *dc,
450 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
452 uint8_t dc_get_current_stream_count(struct dc *dc);
[all …]
/linux/drivers/clk/mvebu/
H A Ddove-divider.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1 // SPDX-License-Identifier: MIT
28 #include "dc.h"
114 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
136 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
139 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
185 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
199 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
715 .dwb_fi_phase = -1, // -1 = disable,
779 ctx->dc->caps.extended_aux_timeout_support); in dcn321_aux_engine_create()
781 return &aux_engine->base; in dcn321_aux_engine_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c47 hws->ctx
50 hws->regs->reg
53 dc->ctx->logger
57 hws->shifts->field_name, hws->masks->field_name
62 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
63 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
64 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
66 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && in patch_address_for_sbs_tb_stereo()
67 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
69 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h1 /* SPDX-License-Identifier: MIT */
31 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
39 void dcn20_calculate_dlg_params(struct dc *dc,
44 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
48 void dcn20_calculate_wm(struct dc *dc,
57 void dcn20_update_bounding_box(struct dc *dc,
62 void dcn20_patch_bounding_box(struct dc *dc,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
75 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
79 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1 // SPDX-License-Identifier: MIT
183 static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
203 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c1 // SPDX-License-Identifier: MIT
79 dc->ctx->logger
98 .dwb_fi_phase = -1, // -1 = disable,
277 return &dio10->base; in dcn303_dio_create()
292 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn303_hubbub_create()
294 vmid->ctx = ctx; in dcn303_hubbub_create()
296 vmid->regs = &vmid_regs[i]; in dcn303_hubbub_create()
297 vmid->shifts = &vmid_shifts; in dcn303_hubbub_create()
298 vmid->masks = &vmid_masks; in dcn303_hubbub_create()
301 return &hubbub3->base; in dcn303_hubbub_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1 // SPDX-License-Identifier: MIT
29 #include "dc.h"
119 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
141 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
144 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
190 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
205 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
724 .dwb_fi_phase = -1, // -1 = disable,
741 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.
790 ctx->dc->caps.extended_aux_timeout_support); in dcn32_aux_engine_create()
[all …]
/linux/drivers/md/bcache/
H A Dwriteback.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 for (i = 0; i < d->nr_stripes; i++) in bcache_dev_sectors_dirty()
54 ret += atomic_read(d->stripe_sectors_dirty + i); in bcache_dev_sectors_dirty()
62 do_div(offset, d->stripe_size); in offset_to_stripe()
64 /* d->nr_stripes is in range [1, INT_MAX] */ in offset_to_stripe()
65 if (unlikely(offset >= d->nr_stripes)) { in offset_to_stripe()
67 offset, d->nr_stripes); in offset_to_stripe()
68 return -EINVAL; in offset_to_stripe()
78 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, in bcache_dev_stripe_dirty() argument
82 int stripe = offset_to_stripe(&dc->disk, offset); in bcache_dev_stripe_dirty()
[all …]
H A Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0
33 "meta-only",
163 out += scnprintf(out, buf + size - out, in bch_snprint_string_list()
166 out[-1] = '\n'; in bch_snprint_string_list()
167 return out - buf; in bch_snprint_string_list()
172 struct cached_dev *dc = container_of(kobj, struct cached_dev, in SHOW() local
175 int wb = dc->writeback_running; in SHOW()
177 #define var(stat) (dc->stat) in SHOW()
182 BDEV_CACHE_MODE(&dc->sb)); in SHOW()
187 dc->cache_readahead_policy); in SHOW()
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
15 #include <video/imx-ipu-v3.h>
16 #include "ipu-prv.h"
58 #define NULL_WAVE (-1)
90 /* The display interface number assigned to this dc channel */
109 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority) in dc_link_event() argument
113 reg = readl(dc->base + DC_RL_CH(event)); in dc_link_event()
116 writel(reg, dc->base + DC_RL_CH(event)); in dc_link_event()
119 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand, in dc_write_tmpl() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c28 #include "dc.h"
578 return &dio10->base; in dcn20_dio_create()
774 return &dpp->base; in dcn20_dpp_create()
794 return &ipp->base; in dcn20_ipp_create()
811 return &opp->base; in dcn20_opp_create()
829 ctx->dc->caps.extended_aux_timeout_support); in dcn20_aux_engine_create()
831 return &aux_engine->base; in dcn20_aux_engine_create()
880 return &mpc20->base; in dcn20_mpc_create()
897 struct dcn20_vmid *vmid = &hubbub->vmid[i]; in dcn20_hubbub_create()
899 vmid->ctx = ctx; in dcn20_hubbub_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c28 #include "dc.h"
96 dc->ctx->logger
727 .dwb_fi_phase = -1, // -1 = disable,
764 return &dpp->base; in dcn30_dpp_create()
784 return &opp->base; in dcn30_opp_create()
802 ctx->dc->caps.extended_aux_timeout_support); in dcn30_aux_engine_create()
804 return &aux_engine->base; in dcn30_aux_engine_create()
859 return &mpc30->base; in dcn30_mpc_create()
878 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn30_hubbub_create()
880 vmid->ctx = ctx; in dcn30_hubbub_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A DMakefile1 # SPDX-License-Identifier: MIT */
41 ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
42 frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
46 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0
47 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_core
48 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_mcg/
49 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_dpmm/
50 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_pmo/
51 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/
52 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/inc
[all …]

12345678910>>...37