Lines Matching +full:dc +full:- +full:dc
2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
118 // for example, 1080p -> 8K is 4.0, or 4000 raw value
126 // for example, 8K -> 1080p is 0.25, or 250 raw value
138 * DOC: color-management-caps
143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
166 * struct dpp_color_caps - color pipeline capabilities for display pipe and
171 * just plain 256-entry lookup
180 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
181 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
182 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
230 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
240 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
259 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
437 * re-programming however do not affect bandwidth consumption or clock
459 struct dc;
464 bool (*get_dcc_compression_cap)(const struct dc *dc,
467 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
480 /* Structure to hold configuration flags set by dm at dc creation. */
583 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
584 INGAME_FAMS_DISABLE, // disable in-game fams
585 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
586 …INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR s…
590 * enum pipe_split_policy - Pipe split strategy supported by DCN
593 * default, DC favors MPC_SPLIT_DYNAMIC.
597 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
598 * pipe in order to bring the best trade-off between performance and
604 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
610 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
612 * user connects to a second display, DC will avoid pipe split.
630 DCN_PWR_STATE_UNKNOWN = -1,
645 * struct dc_clocks - DC pipe clocks
680 * DC has a mechanism that leverage the variable refresh rate to switch
682 * memory clock change and a short vblank window. DC has some
701 * Efficiencies are stored as percentage (0-100)
727 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
728 dm_get_timestamp(dc->ctx) : 0
731 if (dc->debug.bw_val_profile.enable) \
732 dc->debug.bw_val_profile.total_count++
735 if (dc->debug.bw_val_profile.enable) { \
737 voltage_level_tick = dm_get_timestamp(dc->ctx); \
738 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
742 if (dc->debug.bw_val_profile.enable) \
743 voltage_level_tick = dm_get_timestamp(dc->ctx)
746 if (dc->debug.bw_val_profile.enable) \
747 watermark_tick = dm_get_timestamp(dc->ctx)
750 if (dc->debug.bw_val_profile.enable) { \
751 end_tick = dm_get_timestamp(dc->ctx); \
752 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
753 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
755 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
756 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
861 * 15-2: reserved
862 * 31-16: timeout in ms
935 * struct dc_debug_options - DC debug struct
1051 /* TODO - remove once tested */
1170 /* Generic structure that can be used to query properties of DC. More fields
1233 struct dc *dc_create(const struct dc_init_data *init_params);
1234 void dc_hardware_init(struct dc *dc);
1236 int dc_get_vmid_use_vector(struct dc *dc);
1237 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1239 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1240 void dc_init_callbacks(struct dc *dc,
1242 void dc_deinit_callbacks(struct dc *dc);
1243 void dc_destroy(struct dc **dc);
1468 /* private to DC core */
1522 * dc update. The reason is that plane states are overwritten
1523 * with surface updates in dc update. Once they are overwritten
1526 * a valid current state during dc update.
1535 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1609 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1613 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1629 /* Private to DC core */
1631 const struct dc *dc; member
1701 struct dc { struct
1821 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1865 struct dc *dc);
1868 * struct dc_validation_set - Struct to store surface/stream associations for validation
1887 bool dc_validate_boot_timing(const struct dc *dc,
1891 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1893 enum dc_status dc_validate_with_context(struct dc *dc,
1903 struct dc *dc,
1908 struct dc *dc, bool acquire,
1913 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1930 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
1933 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1938 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1943 * return - minimum required timing bandwidth in kbps.
1955 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1958 bool dc_get_edp_link_panel_inst(const struct dc *dc,
1963 void dc_get_edp_links(const struct dc *dc,
1967 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1981 * @reason - Indicate which event triggers this detection. dc may customize
1983 * return false - if detection is not fully completed. This could happen when
1986 * link->connection_type == dc_connection_mst_branch when returning false).
1987 * return true - detection is completed, link has been fully updated with latest
1999 * @dc_link - link the remote sink will be added to.
2000 * @edid - byte array of EDID raw data.
2001 * @len - size of the edid in byte
2002 * @init_data -
2011 * @link - link the sink should be removed from
2012 * @sink - sink to be removed.
2026 * @type - dc_connection_single if connected, dc_connection_none otherwise.
2027 * return - false if an unexpected error occurs, true otherwise.
2038 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
2048 * @link - The link the HPD pin is associated with.
2049 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
2050 * handler once after no HPD change has been detected within dc default HPD
2054 * dc default HPD filtering interval since last HPD event.
2056 * @enable = false - disable hardware HPD filter. HPD event will be queued
2063 * @link_index - index to a link with ddc in i2c mode
2064 * @cmd - i2c command structure
2065 * return - true if success, false otherwise.
2068 struct dc *dc,
2073 * @link_index - index to a link with ddc in i2c mode
2074 * @cmd - i2c command structure
2075 * return - true if success, false otherwise.
2078 struct dc *dc,
2083 * retries or handle error states. The reply is returned in the payload->reply
2085 * transferred,or -1 on a failure.
2092 dc_get_oem_i2c_device(struct dc *dc);
2095 struct dc *dc,
2103 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
2105 * TODO - When defer_handling is true the function will have a different purpose.
2110 * true - Downstream port status changed. DM should call DC to do the
2112 * false - no change in Downstream port status. No further action required
2127 * return true - hpd rx irq should be handled.
2128 * return false - it is safe to ignore hpd rx irq event
2133 * @link - link the hpd irq data associated with
2134 * @hpd_irq_dpcd_data - input hpd irq data
2135 * return - true if hpd irq data indicates a link lost
2141 * @link - link where the hpd irq data should be read from
2142 * @irq_data - output hpd irq data
2143 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
2153 * TODO - in the future we should consider to expand link resume interface to
2168 * return - total effective link bandwidth in kbps.
2186 * return - min hblank size in bytes, 0 if 8b/10b SST.
2193 * @dc: pointer to dc of the dm calling this
2194 * @map: a dc link resource snapshot defined internally to dc.
2206 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2209 * @dc: pointer to dc of the dm calling this
2210 * @map: a dc link resource snapshot defined internally to dc.
2223 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2226 * interface i.e stream_update->dsc_config
2231 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2234 * @link - current detected link
2235 * @req_bw - requested bandwidth in kbps
2236 * @link_settings - returned most optimal link settings that can fit the
2238 * return - false if link can't support requested bandwidth, true if link
2254 * @link - a link with DP RX connection
2255 * return - if stream is committed to this link with MST signal type, type of
2256 * channel coding format dc will choose.
2264 * @link - a link with DP RX connection
2265 * return - max dp link settings the link can enable.
2273 * @link - a link with DP RX connection
2274 * return - highest encoding format link supports.
2280 * @link - a link with dp connector signal type
2281 * return - true if connected, false otherwise
2285 /* Force DP lane settings update to main-link video signal and notify the change
2290 * @lt_settings - a container structure with desired hw_lane_settings
2292 void dc_link_set_drive_settings(struct dc *dc,
2297 * test or debugging purpose. The test pattern will remain until next un-plug.
2299 * @link - active link with DP signal output enabled.
2300 * @test_pattern - desired test pattern to output.
2302 * @test_pattern_color_space - for video test pattern choose a desired color
2304 * @p_link_settings - For PHY pattern choose a desired link settings
2305 * @p_custom_pattern - some test pattern will require a custom input to
2307 * @cust_pattern_size - size of the custom pattern input.
2323 void dc_link_set_preferred_link_settings(struct dc *dc,
2332 * @link_settings - if not NULL, force preferred link settings to the link.
2333 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2335 * passed in, dc resets previous overrides.
2339 void dc_link_set_preferred_training_settings(struct dc *dc,
2345 /* return - true if FEC is supported with connected DP RX, false otherwise */
2348 /* query FEC enablement policy to determine if FEC will be enabled by dc during
2350 * return - true if FEC should be enabled, false otherwise.
2361 * NOTE: this interface doesn't update dp main-link. Calling this function will
2362 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2365 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2370 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2371 * current value read from extended receiver cap from 02200h - 0220Fh.
2388 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2434 * return - true if trace is initialized and has valid data. False dp trace
2455 * @in_detection - true to get link training end time stamp of last link
2462 /* Get how many link training attempts dc has done with latest sequence.
2463 * @in_detection - true to get link training count of last link
2477 * Send a request from DP-Tx requesting to allocate BW remotely after
2491 * Unplug => de-allocate bw
2506 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *…
2514 /* Sink Interfaces - A sink corresponds to a display output device */
2519 // 8 byte port ID -> ELD.PortID
2521 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2523 // 2 byte product code -> ELD.ProductCode
2575 /* private to DC core */
2609 struct dc *dc,
2612 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2613 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2615 struct dc *dc, uint32_t link_index);
2617 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2622 struct dc *dc,
2624 void dc_resume(struct dc *dc);
2626 void dc_power_down_on_boot(struct dc *dc);
2635 bool dc_is_dmcu_initialized(struct dc *dc);
2637 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_…
2638 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2640 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
2646 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __fu… argument
2647 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) argument
2649 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
2650 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
2651 bool dc_dmub_is_ips_idle_state(struct dc *dc);
2654 void dc_unlock_memory_clock_frequency(struct dc *dc);
2657 void dc_lock_memory_clock_frequency(struct dc *dc);
2659 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2660 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2663 void dc_hardware_release(struct dc *dc);
2666 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2668 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2670 bool dc_set_replay_allow_active(struct dc *dc, bool active);
2672 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
2674 void dc_z10_restore(const struct dc *dc);
2675 void dc_z10_save_init(struct dc *dc);
2677 bool dc_is_dmub_outbox_supported(struct dc *dc);
2678 bool dc_enable_dmub_notifications(struct dc *dc);
2681 struct dc *dc,
2685 void dc_enable_dmub_outbox(struct dc *dc);
2687 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2691 /* Get dc link index from dpia port index */
2692 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2695 bool dc_process_dmub_set_config_async(struct dc *dc,
2700 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2705 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tp…
2707 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2710 void dc_print_dmub_diagnostic_data(const struct dc *dc);
2712 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2728 struct dc *dc,
2733 void dc_disable_accelerated_mode(struct dc *dc);
2738 bool dc_is_cursor_limit_pending(struct dc *dc);
2739 bool dc_can_clear_cursor_limit(struct dc *dc);
2742 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.
2744 * @dc: Pointer to the display core context.
2748 * This function collects and logs underflow-related HW states when underflow happens,
2749 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
2752 void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_d…