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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Ddebugfs.c1 // SPDX-License-Identifier: ISC
29 dev->ibf = !!val; in mt7915_implicit_txbf_set()
39 *val = dev->ibf; in mt7915_implicit_txbf_get()
52 struct mt7915_phy *phy = file->private_data; in mt7915_sys_recovery_set() local
53 struct mt7915_dev *dev = phy->dev; in mt7915_sys_recovery_set()
54 bool band = phy->mt76->band_idx; in mt7915_sys_recovery_set()
60 return -EINVAL; in mt7915_sys_recovery_set()
63 return -EFAULT; in mt7915_sys_recovery_set()
65 if (count && buf[count - 1] == '\n') in mt7915_sys_recovery_set()
66 buf[count - 1] = '\0'; in mt7915_sys_recovery_set()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Ddebugfs.c1 // SPDX-License-Identifier: ISC
31 dev->ibf = !!val; in mt7996_implicit_txbf_set()
41 *val = dev->ibf; in mt7996_implicit_txbf_get()
54 struct mt7996_phy *phy = file->private_data; in mt7996_sys_recovery_set() local
55 struct mt7996_dev *dev = phy->dev; in mt7996_sys_recovery_set()
56 bool band = phy->mt76->band_idx; in mt7996_sys_recovery_set()
62 return -EINVAL; in mt7996_sys_recovery_set()
65 return -EFAULT; in mt7996_sys_recovery_set()
67 if (count && buf[count - 1] == '\n') in mt7996_sys_recovery_set()
68 buf[count - 1] = '\0'; in mt7996_sys_recovery_set()
[all …]
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_aq100x.c2 SPDX-License-Identifier: BSD-2-Clause
66 #define AQ_WRITE_REGS(phy, regs) do { \ argument
69 (void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \
72 #define AQ_READ_REGS(phy, regs) do { \ argument
75 (void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \
83 aq100x_temperature(struct cphy *phy) in aq100x_temperature() argument
87 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) || in aq100x_temperature()
91 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v)) in aq100x_temperature()
98 aq100x_set_defaults(struct cphy *phy) in aq100x_set_defaults() argument
100 return mdio_write(phy, MDIO_DEV_VEND1, AQ_THERMAL_THR, 0x6c00); in aq100x_set_defaults()
[all …]
/freebsd/sys/dev/axgbe/
H A Dxgbe-mdio.c4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
116 #include "xgbe-common.h"
179 switch (pdata->an_mode) { in xgbe_an_enable_interrupts()
204 pdata->hw_if.set_speed(pdata, SPEED_10000); in xgbe_kr_mode()
206 /* Call PHY implementation support to complete rate change */ in xgbe_kr_mode()
207 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); in xgbe_kr_mode()
214 pdata->hw_if.set_speed(pdata, SPEED_2500); in xgbe_kx_2500_mode()
216 /* Call PHY implementation support to complete rate change */ in xgbe_kx_2500_mode()
217 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); in xgbe_kx_2500_mode()
224 pdata->hw_if.set_speed(pdata, SPEED_1000); in xgbe_kx_1000_mode()
[all …]
H A Dxgbe-phy-v2.c116 #include "xgbe-common.h"
142 /* Rate-change complete wait/retry count */
153 /* SFP port max PHY probe retries */
275 * Optical specification compliance - denotes wavelength
306 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
307 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
314 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
315 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
326 /* MDIO PHY reset types */
334 /* Re-driver related definitions */
[all …]
/freebsd/sys/dev/bwn/
H A Dif_bwn_phy_g.c1 /*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
143 if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL) in bwn_has_hwpctl()
145 return (mac->mac_phy.use_hwpctl(mac)); in bwn_has_hwpctl()
151 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_g_attach()
152 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_attach() local
153 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_attach()
166 "%d\n", (_name), error); \ in bwn_phy_g_attach()
171 BWN_PHY_G_READVAR(sc->sc_dev, int8, BHND_NVAR_PA0ITSSIT, &bg); in bwn_phy_g_attach()
172 BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B0, &pab0); in bwn_phy_g_attach()
[all …]
/freebsd/sys/dev/etherswitch/arswitch/
H A Darswitch_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
67 * to the PHY space itself, rather than through the switch
71 arswitch_readphy_external(device_t dev, int phy, int reg) in arswitch_readphy_external() argument
79 ret = (MDIO_READREG(device_get_parent(dev), phy, reg)); in arswitch_readphy_external()
81 "%s: phy=0x%08x, reg=0x%08x, ret=0x%08x\n", in arswitch_readphy_external()
82 __func__, phy, reg, ret); in arswitch_readphy_external()
89 arswitch_writephy_external(device_t dev, int phy, int reg, int data) in arswitch_writephy_external() argument
96 (void) MDIO_WRITEREG(device_get_parent(dev), phy, in arswitch_writephy_external()
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
82 int phy; in ar40xx_phy_tick() local
89 * Loop over; update phy port status here in ar40xx_phy_tick()
91 for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) { in ar40xx_phy_tick()
93 * Port here is PHY, not port! in ar40xx_phy_tick()
95 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1)); in ar40xx_phy_tick()
97 mii = device_get_softc(sc->sc_phys.miibus[phy]); in ar40xx_phy_tick()
101 * status. We may need to clear ATU / change phy config. in ar40xx_phy_tick()
104 (mii->mii_media_status & IFM_ACTIVE) == 0) { in ar40xx_phy_tick()
[all …]
H A Dar40xx_hw_psgmii.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 * Routines that control the ess-psgmii block - the interconnect
77 * between the ess-switch and the external multi-port PHY
85 bus_space_write_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
87 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_write()
88 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE); in ar40xx_hw_psgmii_reg_write()
96 bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
97 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ); in ar40xx_hw_psgmii_reg_read()
98 ret = bus_space_read_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle, in ar40xx_hw_psgmii_reg_read()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
11 - Konstantin Porotchkin <kostap@marvell.com>
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
19 UTMI PHY0 --------/
20 0.D-----0
[all …]
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
H A Dqcom,usb-8x16-phy.txt3 - compatible:
6 Definition: Should contain "qcom,usb-8x16-phy".
8 - reg:
10 Value type: <prop-encoded-array>
11 Definition: USB PHY base address and length of the register map
13 - clocks:
15 Value type: <prop-encoded-array>
16 Definition: See clock-bindings.txt section "consumers". List of
20 - clock-names:
25 - vddcx-supply:
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Ddebugfs.c1 // SPDX-License-Identifier: ISC
11 mt76_wr(dev, dev->mt76.debugfs_reg, val); in mt7615_reg_set()
23 *val = mt76_rr(dev, dev->mt76.debugfs_reg); in mt7615_reg_get()
57 ret = mt76_connac_mcu_chip_config(&dev->mt76); in mt7615_config()
74 mt7615_mac_set_scs(&dev->phy, val); in mt7615_scs_set()
87 *val = dev->phy.scs_en; in mt7615_scs_get()
99 struct mt76_connac_pm *pm = &dev->pm; in mt7615_pm_set()
105 if (!mt7615_firmware_offload(dev) || mt76_is_usb(&dev->mt76)) in mt7615_pm_set()
106 return -EOPNOTSUPP; in mt7615_pm_set()
108 mutex_lock(&dev->mt76.mutex); in mt7615_pm_set()
[all …]
/freebsd/sys/riscv/sifive/
H A Dfu740_pci_dw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
101 #define FUDW_MGMT_READ(_sc, _o) bus_read_4((_sc)->mgmt_res, (_o))
102 #define FUDW_MGMT_WRITE(_sc, _o, _v) bus_write_4((_sc)->mgmt_res, (_o), (_v))
105 { "sifive,fu740-pcie", 1 },
111 fupci_phy_read(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t *val) in fupci_phy_read() argument
116 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg); in fupci_phy_read()
117 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 1); in fupci_phy_read()
121 ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK)); in fupci_phy_read()
125 } while (--timeout > 0); in fupci_phy_read()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp151a-prtt1c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_debugfs.c1 // SPDX-License-Identifier: ISC
7 mt792x_ampdu_stat_read_phy(struct mt792x_phy *phy, in mt792x_ampdu_stat_read_phy() argument
10 struct mt792x_dev *dev = file->private; in mt792x_ampdu_stat_read_phy()
13 if (!phy) in mt792x_ampdu_stat_read_phy()
16 mt792x_mac_update_mib_stats(phy); in mt792x_ampdu_stat_read_phy()
27 seq_printf(file, "Length: %8d | ", bound[0]); in mt792x_ampdu_stat_read_phy()
28 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) in mt792x_ampdu_stat_read_phy()
29 seq_printf(file, "%3d %3d | ", bound[i] + 1, bound[i + 1]); in mt792x_ampdu_stat_read_phy()
33 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); in mt792x_ampdu_stat_read_phy()
36 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); in mt792x_ampdu_stat_read_phy()
[all …]
/freebsd/sys/cam/scsi/
H A Dsmp_all.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 * $Id: //depot/users/kenm/FreeBSD-test/sys/cam/scsi/smp_all.c#4 $
92 {SMP_FR_PHY_DOES_NOT_EXIST, "Phy Does Not Exist"},
94 {SMP_FR_PHY_DOES_NOT_SUP_SATA, "Phy Does Not Support SATA"},
95 {SMP_FR_UNKNOWN_PHY_OP, "Unknown Phy Operation"},
96 {SMP_FR_UNKNOWN_PHY_TEST_FUNC, "Unknown Phy Test Function"},
97 {SMP_FR_PHY_TEST_FUNC_INPROG, "Phy Test Function In Progress"},
98 {SMP_FR_PHY_VACANT, "Phy Vacant"},
99 {SMP_FR_UNKNOWN_PHY_EVENT_SRC, "Unknown Phy Event Source"},
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852b_rfk.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
8 #include "phy.h"
200 "[RFK]backup rf S%d reg : %x, value =%x\n", rf_path, in _rfk_backup_rf_reg()
229 "[RFK]restore rf S%d reg: %x, value =%x\n", rf_path, in _rfk_restore_rf_reg()
269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\ in _iqk_check_cal()
293 _set_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _set_rx_dck() argument
302 _rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _rx_dck() argument
1384 _iqk_get_ch_info(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 path) _iqk_get_ch_info() argument
1713 _dpk_one_shot(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw8852b_dpk_id id) _dpk_one_shot() argument
1755 _dpk_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_rx_dck() argument
1762 _dpk_information(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_information() argument
1787 _dpk_bb_afe_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kpath) _dpk_bb_afe_setting() argument
1804 _dpk_bb_afe_restore(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kpath) _dpk_bb_afe_restore() argument
1841 _dpk_lbk_rxiqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_lbk_rxiqk() argument
2025 _dpk_sync(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_sync() argument
2102 _dpk_gainloss(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_gainloss() argument
2109 _dpk_kip_preset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_kip_preset() argument
2126 _dpk_kip_set_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 txagc) _dpk_kip_set_txagc() argument
2137 _dpk_kip_set_rxagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_kip_set_rxagc() argument
2155 _dpk_set_offset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,s8 gain_offset) _dpk_set_offset() argument
2217 _dpk_agc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 init_txagc,bool loss_only) _dpk_agc() argument
2364 _dpk_idl_mpa(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 gain) _dpk_idl_mpa() argument
2378 _dpk_fill_result(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 gain,u8 txagc) _dpk_fill_result() argument
2417 _dpk_reload_check(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_reload_check() argument
2444 _dpk_main(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 gain) _dpk_main() argument
2493 _dpk_cal_select(struct rtw89_dev * rtwdev,bool force,enum rtw89_phy_idx phy,u8 kpath) _dpk_cal_select() argument
2545 _dpk_bypass_check(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _dpk_bypass_check() argument
2567 _dpk_force_bypass(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _dpk_force_bypass() argument
2579 _dpk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool force) _dpk() argument
2696 _set_dpd_backoff(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _set_dpd_backoff() argument
2723 _tssi_rf_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_rf_setting() argument
2735 _tssi_set_sys(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_sys() argument
2754 _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_ini_txpwr_ctrl_bb() argument
2763 _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2771 _tssi_set_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_dck() argument
2779 _tssi_set_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_tmeter_tbl() argument
2937 _tssi_set_dac_gain_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_dac_gain_tbl() argument
2945 _tssi_slope_cal_org(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_slope_cal_org() argument
2961 _tssi_alignment_default(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,bool all) _tssi_alignment_default() argument
3019 _tssi_set_tssi_slope(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_tssi_slope() argument
3027 _tssi_set_tssi_track(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_tssi_track() argument
3037 _tssi_set_txagc_offset_mv_avg(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_txagc_offset_mv_avg() argument
3049 _tssi_enable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _tssi_enable() argument
3101 _tssi_disable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _tssi_disable() argument
3232 _tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_get_ofdm_de() argument
3268 _tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_get_ofdm_trim_de() argument
3306 _tssi_set_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _tssi_set_efuse_to_de() argument
3385 _tssi_alimentk_done(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_alimentk_done() argument
3420 _tssi_hw_tx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u16 cnt,u16 period,s16 pwr_dbm,u8 enable) _tssi_hw_tx() argument
3446 _tssi_backup_bb_registers(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const u32 reg[],u32 reg_backup[],u32 reg_num) _tssi_backup_bb_registers() argument
3461 _tssi_reload_bb_registers(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const u32 reg[],u32 reg_backup[],u32 reg_num) _tssi_reload_bb_registers() argument
3494 _tssi_get_cw_report(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const s16 * power,u32 * tssi_cw_rpt) _tssi_get_cw_report() argument
3568 _tssi_alimentk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_alimentk() argument
3819 rtw8852b_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool hwtx_en) rtw8852b_tssi() argument
3856 rtw8852b_tssi_scan(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) rtw8852b_tssi_scan() argument
3896 rtw8852b_tssi_default_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool enable) rtw8852b_tssi_default_txagc() argument
3987 _ctrl_bw(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_bandwidth bw) _ctrl_bw() argument
4138 _rxbb_bw(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_bandwidth bw) _rxbb_bw() argument
4154 rtw8852b_ctrl_bw_ch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 central_ch,enum rtw89_band band,enum rtw89_bandwidth bw) rtw8852b_ctrl_bw_ch() argument
[all...]
H A Drtw8852a_rfk.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
8 #include "phy.h"
17 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n", in _kpath()
18 rtwdev->dbcc_en, phy_idx); in _kpath()
20 if (!rtwdev->dbcc_en) in _kpath()
58 "[IQK]backup rf S%d reg : %x, value =%x\n", rf_path, in _rfk_backup_rf_reg()
87 "[IQK]restore rf S%d reg: %x, value =%x\n", rf_path, in _rfk_restore_rf_reg()
106 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", in _wait_rx_mode()
113 struct rtw89_dack_info *dack = &rtwdev->dack; in _dack_dump()
[all …]
H A Drtw8852c_rfk.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
8 #include "phy.h"
81 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n", in _kpath()
82 rtwdev->dbcc_e in _kpath()
1323 _iqk_get_ch_info(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 path) _iqk_get_ch_info() argument
1732 _set_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 path,bool is_afe) _set_rx_dck() argument
1867 _dpk_one_shot(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw8852c_dpk_id id) _dpk_one_shot() argument
1902 _dpk_information(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_information() argument
1927 _dpk_bb_afe_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kpath) _dpk_bb_afe_setting() argument
2000 _dpk_kip_restore(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_kip_restore() argument
2010 _dpk_lbk_rxiqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_lbk_rxiqk() argument
2211 _dpk_kip_set_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 dbm,bool set_from_bb) _dpk_kip_set_txagc() argument
2223 _dpk_gainloss(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_gainloss() argument
2280 _dpk_kip_set_rxagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_kip_set_rxagc() argument
2317 _dpk_agc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 init_xdbm,u8 loss_only) _dpk_agc() argument
2447 _dpk_idl_mpa(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_idl_mpa() argument
2496 _dpk_reload_check(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _dpk_reload_check() argument
2529 _dpk_kip_preset_8852c(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_kip_preset_8852c() argument
2567 _dpk_gain_normalize_8852c(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,bool is_execute) _dpk_gain_normalize_8852c() argument
2614 _dpk_on(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx) _dpk_on() argument
2636 _dpk_main(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 gain) _dpk_main() argument
2691 _dpk_cal_select(struct rtw89_dev * rtwdev,bool force,enum rtw89_phy_idx phy,u8 kpath) _dpk_cal_select() argument
2761 _dpk_bypass_check(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _dpk_bypass_check() argument
2784 _dpk_force_bypass(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _dpk_force_bypass() argument
2796 _dpk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool force) _dpk() argument
2896 _tssi_set_sys(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_sys() argument
2914 _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_ini_txpwr_ctrl_bb() argument
2923 _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2931 _tssi_set_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_dck() argument
2950 _tssi_set_bbgain_split(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_bbgain_split() argument
2958 _tssi_set_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_tmeter_tbl() argument
3144 _tssi_slope_cal_org(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_slope_cal_org() argument
3161 _tssi_set_aligk_default(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_aligk_default() argument
3187 _tssi_set_slope(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_slope() argument
3195 _tssi_run_slope(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_run_slope() argument
3203 _tssi_set_track(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_track() argument
3212 _tssi_set_txagc_offset_mv_avg(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_set_txagc_offset_mv_avg() argument
3220 _tssi_enable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _tssi_enable() argument
3249 _tssi_disable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _tssi_disable() argument
3572 _tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_get_ofdm_de() argument
3636 _tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path) _tssi_get_ofdm_trim_de() argument
3702 _tssi_set_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) _tssi_set_efuse_to_de() argument
3844 _ctrl_bw(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_bandwidth bw) _ctrl_bw() argument
3912 _ctrl_ch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 central_ch,enum rtw89_band band) _ctrl_ch() argument
3938 _rxbb_bw(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_bandwidth bw) _rxbb_bw() argument
4036 rtw8852c_ctrl_bw_ch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 central_ch,enum rtw89_band band,enum rtw89_bandwidth bw) rtw8852c_ctrl_bw_ch() argument
4108 _rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool is_afe,u8 retry_limit) _rx_dck() argument
4162 rtw8852c_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool is_afe) rtw8852c_rx_dck() argument
4242 rtw8852c_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) rtw8852c_tssi() argument
4277 rtw8852c_tssi_scan(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy) rtw8852c_tssi_scan() argument
4314 rtw8852c_tssi_default_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool enable) rtw8852c_tssi_default_txagc() argument
[all...]
H A Drtw8851b_rfk.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
8 #include "phy.h"
180 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", in _wait_rx_mode()
223 struct rtw89_dack_info *dack = &rtwdev->dack; in _addck_backup()
227 dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0); in _addck_backup()
228 dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1); in _addck_backup()
233 struct rtw89_dack_info *dack = &rtwdev->dack; in _addck_reload()
235 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL1, dack->addck_d[0][0]); in _addck_reload()
236 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL0, dack->addck_d[0][1]); in _addck_reload()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-phy-db.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2020-2021 Intel Corporation
10 #include "iwl-drv.h"
11 #include "iwl-phy-db.h"
12 #include "iwl-debug.h"
13 #include "iwl-op-mode.h"
14 #include "iwl-trans.h"
22 * struct iwl_phy_db - stores phy configuration and calibration data.
24 * @cfg: phy configuration.
68 phy_db->trans = trans; in iwl_phy_db_init()
[all …]
/freebsd/sys/dev/mps/
H A Dmps_table.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
113 {"PHY disabled", 0x01},
136 {"SMP Phy Control Link Reset", 0x03},
139 {"I-T Nexus Loss Timer", 0x06},
141 {"PHY Test Function", 0x08},
256 MPS_PRINTFIELD(sc, facts, IOCNumber, %d); in mps_print_iocfacts()
258 MPS_PRINTFIELD(sc, facts, MaxChainDepth, %d); in mps_print_iocfacts()
260 mps_describe_table(mps_whoinit_names, facts->WhoInit)); in mps_print_iocfacts()
261 MPS_PRINTFIELD(sc, facts, NumberOfPorts, %d); in mps_print_iocfacts()
[all …]
/freebsd/sys/dev/bwi/
H A Dbwiphy.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
137 struct bwi_softc *sc = mac->mac_sc; in bwi_phy_write()
146 struct bwi_softc *sc = mac->mac_sc; in bwi_phy_read()
155 struct bwi_softc *sc = mac->mac_sc; in bwi_phy_attach()
156 struct bwi_phy *phy = &mac->mac_phy; in bwi_phy_attach() local
161 /* Get PHY type/revision/version */ in bwi_phy_attach()
166 device_printf(sc->sc_dev, "PHY: type %d, rev %d, ver %d\n", in bwi_phy_attach()
170 * Verify whether the revision of the PHY type is supported in bwi_phy_attach()
171 * Convert PHY type to ieee80211_phymode in bwi_phy_attach()
[all …]

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