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/freebsd/contrib/opencsd/decoder/source/
H A Dtrc_core_arch_map.cpp44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
53 { "Cortex-A35", { ARCH_V8, profile_CortexA } },
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
28 ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FPUVersion::VFPV3_FP16,
30 ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None,
32 ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16,
36 ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FPUVersion::VFPV3_FP16,
40 ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None,
42 ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FPUVersion::VFPV4,
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/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
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H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
[all …]
H A Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,corstone1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11 - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
25 seamless integration of the optional CryptoCell™-312 cryptographic
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H A Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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/freebsd/sys/contrib/device-tree/Bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
/freebsd/share/mk/
H A Dbsd.cpu.mk34 CPUTYPE = skylake-avx512
35 . elif ${CPUTYPE} == "core-avx2"
37 . elif ${CPUTYPE} == "core-avx-i"
39 . elif ${CPUTYPE} == "corei7-avx"
65 . elif ${CPUTYPE} == "p-m"
66 CPUTYPE = pentium-m
72 CPUTYPE = pentium-mmx
83 # http://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
84 # http://gcc.gnu.org/onlinedocs/gcc/RS-6000-and-PowerPC-Options.html
85 # http://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
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/freebsd/contrib/opencsd/decoder/include/common/
H A Dtrc_core_arch_map.h49 * Valid core names are:-
50 * - Cortex-Axx : where xx = 5,7,12,15,17,32,35,53,55,57,65,72,73,75,76,77;
51 * - Cortex-Rxx : where xx = 5,7,8,52;
52 * - Cortex-Mxx : where xx = 0,0+,3,4,23,33;
54 * Valid architecture profile names are:-
55 * - ARMv7-A, ARMv7-R, ARMv7-M;
56 * - ARMv8-A, ARMv8.x-A, ARMv8-R, ARMv8-M;
57 * - ARM-AA64, ARM-aa64
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td1 //===----------------------------------------------------------------------===//
6 def ModeThumb : SubtargetFeature<"thumb-mode", "IsThumb",
10 def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
14 //===----------------------------------------------------------------------===//
21 string TargetFeatureName, // String used for -target-feature.
32 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
38 // extension) and MVE (even in the integer-only version).
40 "Enable 16-bit FP registers",
44 "Enable 64-bit FP registers",
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/freebsd/share/examples/etc/
H A Dmake.conf25 # generated code. This controls processor-specific optimizations in
33 # bdver1, btver2, btver1, amdfam10, opteron-sse3,
34 # athlon64-sse3, k8-sse3, opteron, athlon64, athlon-fx,
35 # k8, athlon-mp, athlon-xp, athlon-4, athlon-tbird,
36 # athlon, k7, geode, k6-3, k6-2, k6
38 # cascadelake, tremont, goldmont-plus, icelake-server,
39 # icelake-client, cannonlake, knm, skylake-avx512, knl,
43 # pentium3m, pentium3, pentium-m, pentium2, pentiumpro,
44 # pentium-mmx, pentium, i486
45 # (VIA CPUs) c7, c3-2, c3
[all …]
/freebsd/sys/sys/
H A Dpmc.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2008, Joseph Koshy
48 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
51 * Kernel<->userland API version number [MMmmpppp]
116 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \
117 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \
118 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \
119 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \
120 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \
[all …]
/freebsd/tools/boot/
H A Dfull-test.sh4 # cache - Cached binaries that we have downloaded
5 # trees - binary trees that we use to make image
7 # images - bootable images that we use to test
9 # bios - cached bios images (as well as 'vars' files when we start testing
11 # scripts - generated scripts that uses images to run the tests.
16 # use qemu-system-XXXX to boot. They all boot the same thing at the moment:
23 # eg https://download.freebsd.org/releases/amd64/amd64/ISO-IMAGES/14.2/FreeBSD-14.2-RELEASE-amd64-b…
25 : ${STAND_ROOT:="${HOME}/stand-test-root"}
38 if [ -f ${t}/tools/build/make.py ]; then
40 case $(uname -m) in
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 secondary-boot-reg = <0xffff0400>;
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6779.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/mt6779-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "arm,psci-0.2";
25 #address-cells = <1>;
[all …]
H A Dmt7988a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a73";
[all …]
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DArchSpec.cpp1 //===-- ArchSpec.cpp ------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 #include "lldb/lldb-defines.h"
193 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
234 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
236 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
279 //===----------------------------------------------------------------------===//
286 // clang-format off
348 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
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/freebsd/sys/contrib/device-tree/src/arm64/zte/
H A Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DARMBuildAttributes.h1 //===-- ARMBuildAttributes.h - ARM Build Attributes -------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // ELF for the ARM Architecture r2.09 - November 30, 2012
16 //===----------------------------------------------------------------------===//
103 v7 = 10, // e.g. Cortex A8, Cortex M3
104 v6_M = 11, // e.g. Cortex M1
108 v8_R = 15, // e.g. Cortex R52
116 Not_Applicable = 0, // pre v7, or cross-profile code
117 ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8)
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dfirmware1 #------------------------------------------------------------------------------
6 # https://github.com/MatrixEditor/frontier-smart-api/blob/main/docs/firmware-2.0.md#11-header-struc…
7 # examples: https://github.com/cweiske/frontier-silicon-firmwares
25 0 string --=</Begin\x20HP\x20Signed
31 >75 string label_HPE-HPB-BMC-ILO5-4096
36 # from https://github.com/open-power/skiboot/blob/master/libstb/container.h
47 # ARM Cortex-M vector table
49 # URL: https://developer.arm.com/documentation/100701/0200/Exception-properties
52 # Function pointers must be in Thumb-mode and before 0x20000000 (4*5 bits match)
58 # Match Cortex-M reserved sections (0x00000000 or 0xFFFFFFFF)
[all …]
/freebsd/stand/kboot/
H A DREADME4 (2) mkdir -p .../initrd/boot/defaults
9 (7) find . | sort | cpio -o -H newc | gzip > /tmp/initrd.cpio
11 (9) qemu-system-x86_64 -kernel ~/vmlinuz-5.19.0-051900-generic \
12 -initrd /tmp/initrd.cpio \
13 -m 256m -nographic \
14 -monitor telnet::4444,server,nowait -serial stdio \
15 -append "console=ttyS0"
16 (though you may need more than 256M of ram to actually boot FreeBSD and do
28 For #8, see https://kernel.ubuntu.com/~kernel-ppa/mainline/ to download
33 qemu-system-aarch64 -m 1024 -cpu cortex-a57 -M virt \
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j722s.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
13 #include "k3-pinctrl.h"
18 interrupt-parent = <&gic500>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]

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