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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
26 compatible = "arm,cortex-a9-scu";
H A Darm,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
29 - arm,cortex-a5-scu
[all …]
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-jun
[all...]
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Darm,twd.txt3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
[all …]
H A Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
H A Darm,global_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
[all …]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Damlogic-a5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "amlogic-a4-common.dtsi"
7 #include <dt-bindings/power/amlogic,a5-pwrc.h>
10 #address-cells = <2>;
11 #size-cells = <0>;
15 compatible = "arm,cortex-a55";
17 enable-method = "psci";
22 compatible = "arm,cortex-a55";
24 enable-method = "psci";
29 compatible = "arm,cortex-a55";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMProcessors.td4 //===----------------------------------------------------------------------===//
8 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
9 "Cortex-A5 ARM processors", []>;
11 "Cortex-A7 ARM processors", []>;
13 "Cortex-A8 ARM processors", []>;
15 "Cortex-A9 ARM processors", []>;
17 "Cortex-A12 ARM processors", []>;
19 "Cortex-A15 ARM processors", []>;
21 "Cortex-A17 ARM processors", []>;
23 "Cortex-A32 ARM processors", []>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
[all …]
/freebsd/contrib/opencsd/decoder/source/
H A Dtrc_core_arch_map.cpp44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
53 { "Cortex-A35", { ARCH_V8, profile_CortexA } },
[all …]
/freebsd/sys/arm/arm/
H A Dpmu_fdt.c1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
45 {"arm,armv8-pmuv3", 1},
46 {"arm,cortex-a77-pmu", 1},
47 {"arm,cortex-a76-pmu", 1},
48 {"arm,cortex-a75-pmu", 1},
49 {"arm,cortex-a73-pmu", 1},
50 {"arm,cortex-a72-pmu", 1},
51 {"arm,cortex-a65-pmu", 1},
52 {"arm,cortex-a57-pmu", 1},
[all …]
H A Dmpcore_timer.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
35 * The ARM Cortex-A9 core can support a global timer plus a private and
40 * The timecount timer uses the global 64-bit counter, whereas the
41 * per-CPU eventtimer uses the private 32-bit counters.
44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
71 /* Private (per-CPU) timer register map */
114 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
115 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
116 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)
[all …]
H A Didentcpu-v6.c3 /*-
76 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
78 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
80 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
82 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
84 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
86 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
88 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
90 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
92 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
[all …]
/freebsd/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-armv4.pl2 # Copyright 2015-2020 The OpenSSL Project Authors. All Rights Reserved.
23 # original .c module was made 32-bit savvy in order to make this
26 # with/without -DECP_NISTZ256_ASM
27 # Cortex-A8 +53-170%
28 # Cortex-A9 +76-205%
29 # Cortex-A15 +100-316%
30 # Snapdragon S4 +66-187%
33 # on benchmark. Lower coefficients are for ECDSA sign, server-side
43 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
44 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
[all …]
/freebsd/share/examples/etc/
H A Dmake.conf25 # generated code. This controls processor-specific optimizations in
33 # bdver1, btver2, btver1, amdfam10, opteron-sse3,
34 # athlon64-sse3, k8-sse3, opteron, athlon64, athlon-fx,
35 # k8, athlon-mp, athlon-xp, athlon-4, athlon-tbird,
36 # athlon, k7, geode, k6-3, k6-2, k6
38 # cascadelake, tremont, goldmont-plus, icelake-server,
39 # icelake-client, cannonlake, knm, skylake-avx512, knl,
43 # pentium3m, pentium3, pentium-m, pentium2, pentiumpro,
44 # pentium-mmx, pentium, i486
45 # (VIA CPUs) c7, c3-2, c3
[all …]
/freebsd/lib/libpmc/
H A Dpmc.31 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
40 The library is implemented using the lower-level facilities offered by
50 .Bl -bullet
53 These PMCs measure events in a whole-system manner, i.e., independent
57 Non-privileged process are allowed to allocate system scope PMCs if the
61 is non-zero.
72 .Bl -bullet
90 The library uses human-readable strings to name the event being
99 Additionally, process-scope PMCs have to be attached to one or more
101 A process-scope PMC may be attached to those target processes
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dexynos4-fimc-is.txt1 Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
3 The FIMC-IS is a subsystem for processing image signal from an image sensor.
4 The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
8 fimc-is node
9 ------------
12 - compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
14 - reg : physical base address and length of the registers set;
15 - interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
16 - clocks : list of clock specifiers, corresponding to entries in
17 clock-names property;
[all …]

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