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/linux/drivers/bcma/
H A Dmain.c36 struct bcma_device *core = container_of(dev, struct bcma_device, dev); in manuf_show() local
37 return sprintf(buf, "0x%03X\n", core->id.manuf); in manuf_show()
43 struct bcma_device *core = container_of(dev, struct bcma_device, dev); in id_show() local
44 return sprintf(buf, "0x%03X\n", core->id.id); in id_show()
50 struct bcma_device *core = container_of(dev, struct bcma_device, dev); in rev_show() local
51 return sprintf(buf, "0x%02X\n", core->id.rev); in rev_show()
57 struct bcma_device *core = container_of(dev, struct bcma_device, dev); in class_show() local
58 return sprintf(buf, "0x%X\n", core->id.class); in class_show()
90 struct bcma_device *core; in bcma_find_core_unit() local
92 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
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H A Dcore.c3 * Core ops
12 static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask, in bcma_core_wait_value() argument
19 val = bcma_aread32(core, reg); in bcma_core_wait_value()
26 bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg); in bcma_core_wait_value()
31 bool bcma_core_is_enabled(struct bcma_device *core) in bcma_core_is_enabled() argument
33 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC)) in bcma_core_is_enabled()
36 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET) in bcma_core_is_enabled()
42 void bcma_core_disable(struct bcma_device *core, u32 flags) in bcma_core_disable() argument
44 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET) in bcma_core_disable()
47 bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300); in bcma_core_disable()
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H A Dhost_pci.c14 static void bcma_host_pci_switch_core(struct bcma_device *core) in bcma_host_pci_switch_core() argument
16 int win2 = core->bus->host_is_pcie2 ? in bcma_host_pci_switch_core()
19 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN, in bcma_host_pci_switch_core()
20 core->addr); in bcma_host_pci_switch_core()
21 pci_write_config_dword(core->bus->host_pci, win2, core->wrap); in bcma_host_pci_switch_core()
22 core->bus->mapped_core = core; in bcma_host_pci_switch_core()
23 bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id); in bcma_host_pci_switch_core()
26 /* Provides access to the requested core. Returns base offset that has to be
28 static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core) in bcma_host_pci_provide_access_to_core() argument
30 switch (core->id.id) { in bcma_host_pci_provide_access_to_core()
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/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2055.h11 #define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */
12 #define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */
13 #define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */
14 #define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */
15 #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
16 #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
17 #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
18 #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
19 #define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */
20 #define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */
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/linux/drivers/staging/media/meson/vdec/
H A Dvdec_hevc.c29 struct amvdec_core *core = sess->core; in vdec_hevc_load_firmware() local
30 struct device *dev = core->dev_dec; in vdec_hevc_load_firmware()
50 mc_addr = dma_alloc_coherent(core->dev, MC_SIZE, &mc_addr_map, in vdec_hevc_load_firmware()
59 amvdec_write_dos(core, HEVC_MPSR, 0); in vdec_hevc_load_firmware()
60 amvdec_write_dos(core, HEVC_CPSR, 0); in vdec_hevc_load_firmware()
62 amvdec_write_dos(core, HEVC_IMEM_DMA_ADR, mc_addr_map); in vdec_hevc_load_firmware()
63 amvdec_write_dos(core, HEVC_IMEM_DMA_COUNT, MC_SIZE / 4); in vdec_hevc_load_firmware()
64 amvdec_write_dos(core, HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); in vdec_hevc_load_firmware()
66 while (i && (readl(core->dos_base + HEVC_IMEM_DMA_CTRL) & 0x8000)) in vdec_hevc_load_firmware()
74 dma_free_coherent(core->dev, MC_SIZE, mc_addr, mc_addr_map); in vdec_hevc_load_firmware()
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H A Dvdec_1.c29 struct amvdec_core *core = sess->core; in vdec_1_load_firmware() local
30 struct device *dev = core->dev_dec; in vdec_1_load_firmware()
48 mc_addr = dma_alloc_coherent(core->dev, MC_SIZE, in vdec_1_load_firmware()
57 amvdec_write_dos(core, MPSR, 0); in vdec_1_load_firmware()
58 amvdec_write_dos(core, CPSR, 0); in vdec_1_load_firmware()
60 amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31)); in vdec_1_load_firmware()
62 amvdec_write_dos(core, IMEM_DMA_ADR, mc_addr_map); in vdec_1_load_firmware()
63 amvdec_write_dos(core, IMEM_DMA_COUNT, MC_SIZE / 4); in vdec_1_load_firmware()
64 amvdec_write_dos(core, IMEM_DMA_CTRL, (0x8000 | (7 << 16))); in vdec_1_load_firmware()
66 while (--i && amvdec_read_dos(core, IMEM_DMA_CTRL) & 0x8000); in vdec_1_load_firmware()
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H A Desparser.c62 struct amvdec_core *core = dev; in esparser_isr() local
64 int_status = amvdec_read_parser(core, PARSER_INT_STATUS); in esparser_isr()
65 amvdec_write_parser(core, PARSER_INT_STATUS, int_status); in esparser_isr()
68 amvdec_write_parser(core, PFIFO_RD_PTR, 0); in esparser_isr()
69 amvdec_write_parser(core, PFIFO_WR_PTR, 0); in esparser_isr()
81 static int vp9_update_header(struct amvdec_core *core, struct vb2_buffer *buf) in vp9_update_header() argument
97 dev_warn(core->dev, "%s: unable to update header\n", __func__); in vp9_update_header()
136 dev_warn(core->dev, "%s: unable to update header\n", __func__); in vp9_update_header()
170 dev_dbg(core->dev, "%s: data has gaps, setting to 0\n", in vp9_update_header()
175 dev_err(core->dev, "%s: data overwritten\n", __func__); in vp9_update_header()
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/linux/drivers/clk/at91/
H A Dclk-sam9x60-pll.c38 struct sam9x60_pll_core core; member
45 struct sam9x60_pll_core core; member
52 #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core) argument
53 #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core) argument
74 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); in sam9x60_frac_pll_recalc_rate() local
75 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_recalc_rate()
81 if (core->layout->div2) in sam9x60_frac_pll_recalc_rate()
87 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) in sam9x60_frac_pll_set() argument
89 struct sam9x60_frac *frac = to_sam9x60_frac(core); in sam9x60_frac_pll_set()
90 struct regmap *regmap = core->regmap; in sam9x60_frac_pll_set()
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/linux/include/trace/events/
H A Dclk.h17 TP_PROTO(struct clk_core *core),
19 TP_ARGS(core),
22 __string( name, core->name )
34 TP_PROTO(struct clk_core *core),
36 TP_ARGS(core)
41 TP_PROTO(struct clk_core *core),
43 TP_ARGS(core)
48 TP_PROTO(struct clk_core *core),
50 TP_ARGS(core)
55 TP_PROTO(struct clk_core *core),
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/linux/tools/perf/pmu-events/arch/x86/
H A Dmapfile.csv2 GenuineIntel-6-(97|9A|B7|BA|BF),v1.39,alderlake,core
3 GenuineIntel-6-BE,v1.39,alderlaken,core
4 GenuineIntel-6-C[56],v1.17,arrowlake,core
5 GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
6 GenuineIntel-6-(3D|47),v30,broadwell,core
7 GenuineIntel-6-56,v12,broadwellde,core
8 GenuineIntel-6-4F,v23,broadwellx,core
9 GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
10 GenuineIntel-6-DD,v1.02,clearwaterforest,core
11 GenuineIntel-6-9[6C],v1.05,elkhartlake,core
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/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_cec.c56 static void hdmi_cec_received_msg(struct hdmi_core_data *core) in hdmi_cec_received_msg() argument
58 u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
71 msg.msg[0] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
73 msg.msg[1] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
79 hdmi_read_reg(core->base, reg); in hdmi_cec_received_msg()
82 cec_received_msg(core->adap, &msg); in hdmi_cec_received_msg()
85 hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1); in hdmi_cec_received_msg()
87 while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1) in hdmi_cec_received_msg()
93 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
97 void hdmi4_cec_irq(struct hdmi_core_data *core) in hdmi4_cec_irq() argument
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/linux/drivers/media/platform/amphion/
H A Dvpu_rpc.h9 #include <media/videobuf2-core.h>
27 struct vpu_core *core; member
47 int (*boot_core)(struct vpu_core *core);
48 int (*shutdown_core)(struct vpu_core *core);
49 int (*restore_core)(struct vpu_core *core);
50 int (*get_power_state)(struct vpu_core *core);
51 int (*on_firmware_loaded)(struct vpu_core *core);
114 struct vpu_iface_ops *vpu_core_get_iface(struct vpu_core *core);
116 int vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size);
118 static inline bool vpu_iface_check_codec(struct vpu_core *core) in vpu_iface_check_codec() argument
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H A Dvpu_cmds.c65 static int vpu_cmd_send(struct vpu_core *core, struct vpu_rpc_event *pkt) in vpu_cmd_send() argument
69 ret = vpu_iface_send_cmd(core, pkt); in vpu_cmd_send()
75 vpu_mbox_send_type(core, COMMAND); in vpu_cmd_send()
97 ret = vpu_iface_pack_cmd(inst->core, cmd->pkt, inst->id, id, data); in vpu_alloc_cmd()
130 ret = vpu_cmd_send(inst->core, cmd->pkt); in vpu_session_process_cmd()
165 struct vpu_core *core; in vpu_request_cmd() local
168 if (!inst || !inst->core) in vpu_request_cmd()
171 core = inst->core; in vpu_request_cmd()
176 mutex_lock(&core->cmd_lock); in vpu_request_cmd()
185 mutex_unlock(&core->cmd_lock); in vpu_request_cmd()
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/linux/tools/perf/tests/
H A Dparse-events.c59 * Returns number of core PMUs if the evlist has >1 core PMU, otherwise in num_core_entries()
60 * returns 1. The number of core PMUs is needed as wild carding can in num_core_entries()
61 * open an event for each core PMU. If the events were opened with a in num_core_entries()
79 return (evsel->core.attr.config & PERF_HW_EVENT_MASK) == expected_config; in test_hw_config()
112 TEST_ASSERT_EVLIST("wrong number of entries", 1 == evlist->core.nr_entries, evlist); in test__checkevent_tracepoint()
114 TEST_ASSERT_EVSEL("wrong type", PERF_TYPE_TRACEPOINT == evsel->core.attr.type, evsel); in test__checkevent_tracepoint()
116 PERF_TP_SAMPLE_TYPE == evsel->core.attr.sample_type, evsel); in test__checkevent_tracepoint()
117 TEST_ASSERT_EVSEL("wrong sample_period", 1 == evsel->core.attr.sample_period, evsel); in test__checkevent_tracepoint()
125 TEST_ASSERT_EVLIST("wrong number of entries", evlist->core in test__checkevent_tracepoint_multi()
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/linux/drivers/net/can/esd/
H A Desdacc.c39 /* Two bit wide command masks to mask or unmask a single core IRQ */
47 static void acc_resetmode_enter(struct acc_core *core) in acc_resetmode_enter() argument
49 acc_set_bits(core, ACC_CORE_OF_CTRL, in acc_resetmode_enter()
53 acc_resetmode_entered(core); in acc_resetmode_enter()
56 static void acc_resetmode_leave(struct acc_core *core) in acc_resetmode_leave() argument
58 acc_clear_bits(core, ACC_CORE_OF_CTRL, in acc_resetmode_leave()
62 acc_resetmode_entered(core); in acc_resetmode_leave()
65 static void acc_txq_put(struct acc_core *core, u32 acc_id, u32 acc_dlc, in acc_txq_put() argument
68 acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1, in acc_txq_put()
70 acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_0, in acc_txq_put()
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/linux/arch/parisc/kernel/
H A Dhardware.c317 {HPHW_A_DMA, 0x005, 0x00039, 0x80, "KittyHawk CSY Core SCSI"},
323 {HPHW_A_DMA, 0x005, 0x0003B, 0x80, "KittyHawk CSY Core FW-SCSI"},
344 {HPHW_A_DMA, 0x015, 0x00089, 0x80, "KittyHawk GSY Core FW-SCSI"},
348 {HPHW_A_DMA, 0x032, 0x00089, 0x80, "Raven T' Core FW-SCSI"},
349 {HPHW_A_DMA, 0x03B, 0x00089, 0x80, "Raven U/L2 Core FW-SCSI"},
350 {HPHW_A_DMA, 0x03C, 0x00089, 0x80, "Merlin 132 Core FW-SCSI"},
351 {HPHW_A_DMA, 0x03D, 0x00089, 0x80, "Merlin 160 Core FW-SCSI"},
352 {HPHW_A_DMA, 0x044, 0x00089, 0x80, "Mohawk Core FW-SCSI"},
377 {HPHW_BA, 0x004, 0x00070, 0x0, "Cobra Core BA"},
378 {HPHW_BA, 0x005, 0x00070, 0x0, "Coral Core BA"},
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/linux/sound/soc/qcom/qdsp6/
H A Dq6core.c72 struct q6core *core = dev_get_drvdata(&adev->dev); in q6core_callback() local
83 core->get_version_supported = false; in q6core_callback()
84 core->resp_received = true; in q6core_callback()
88 core->fwk_version_supported = false; in q6core_callback()
89 core->resp_received = true; in q6core_callback()
93 core->get_state_supported = false; in q6core_callback()
94 core->resp_received = true; in q6core_callback()
104 core->fwk_version = kmemdup(data->payload, in q6core_callback()
108 if (!core->fwk_version) in q6core_callback()
111 core->fwk_version_supported = true; in q6core_callback()
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/linux/drivers/iio/common/cros_ec_sensors/
H A Dcros_ec_sensors.c30 struct cros_ec_sensors_core_state core; member
46 mutex_lock(&st->core.cmd_lock); in cros_ec_sensors_read()
50 ret = st->core.read_ec_sensors_data(indio_dev, 1 << idx, &data); in cros_ec_sensors_read()
57 st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_OFFSET; in cros_ec_sensors_read()
58 st->core.param.sensor_offset.flags = 0; in cros_ec_sensors_read()
60 ret = cros_ec_motion_send_host_cmd(&st->core, 0); in cros_ec_sensors_read()
66 st->core.calib[i].offset = in cros_ec_sensors_read()
67 st->core.resp->sensor_offset.offset[i]; in cros_ec_sensors_read()
69 *val = st->core.calib[idx].offset; in cros_ec_sensors_read()
72 st->core.param.cmd = MOTIONSENSE_CMD_SENSOR_SCALE; in cros_ec_sensors_read()
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/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c42 * @core: pointer to the Stingray PCIe PHY core control
47 struct sr_pcie_phy_core *core; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
76 * core and associated serdes has been enabled as RC and is available for use
81 /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
120 static u32 pipemux_strap_read(struct sr_pcie_phy_core *core) in pipemux_strap_read() argument
130 pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET); in pipemux_strap_read()
133 regmap_read(core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, &pipemux); in pipemux_strap_read()
142 * Given a PIPEMUX strap and PCIe core index, this function returns true if the
143 * PCIe core needs to be enabled
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/linux/include/linux/bcma/
H A Dbcma.h44 u8 (*read8)(struct bcma_device *core, u16 offset);
45 u16 (*read16)(struct bcma_device *core, u16 offset);
46 u32 (*read32)(struct bcma_device *core, u16 offset);
47 void (*write8)(struct bcma_device *core, u16 offset, u8 value);
48 void (*write16)(struct bcma_device *core, u16 offset, u16 value);
49 void (*write32)(struct bcma_device *core, u16 offset, u32 value);
51 void (*block_read)(struct bcma_device *core, void *buffer,
53 void (*block_write)(struct bcma_device *core, const void *buffer,
57 u32 (*aread32)(struct bcma_device *core, u16 offset);
58 void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
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/linux/drivers/media/pci/cx88/
H A Dcx88-i2c.c46 struct cx88_core *core = data; in cx8800_bit_setscl() local
49 core->i2c_state |= 0x02; in cx8800_bit_setscl()
51 core->i2c_state &= ~0x02; in cx8800_bit_setscl()
52 cx_write(MO_I2C, core->i2c_state); in cx8800_bit_setscl()
58 struct cx88_core *core = data; in cx8800_bit_setsda() local
61 core->i2c_state |= 0x01; in cx8800_bit_setsda()
63 core->i2c_state &= ~0x01; in cx8800_bit_setsda()
64 cx_write(MO_I2C, core->i2c_state); in cx8800_bit_setsda()
70 struct cx88_core *core = data; in cx8800_bit_getscl() local
79 struct cx88_core *core = data; in cx8800_bit_getsda() local
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/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-power.json11 "BriefDescription": "Core C State Transition Cycles",
16 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
20 "BriefDescription": "Core C State Transition Cycles",
25 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
29 "BriefDescription": "Core C State Transition Cycles",
34 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
38 "BriefDescription": "Core C State Transition Cycles",
43 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
47 "BriefDescription": "Core C State Transition Cycles",
52 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-power.json11 "BriefDescription": "Core C State Transition Cycles",
16 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
20 "BriefDescription": "Core C State Transition Cycles",
25 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
29 "BriefDescription": "Core C State Transition Cycles",
34 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
38 "BriefDescription": "Core C State Transition Cycles",
43 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
47 "BriefDescription": "Core C State Transition Cycles",
52 …Description": "Number of cycles spent performing core C state transitions. There is one event per…
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Ddatasource.json15 …The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a deman…
20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du…
60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
70 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
80 …processor's instruction cache was reloaded from a source beyond the local core's L1 due to a deman…
85 …The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a deman…
90 …processor's instruction cache was reloaded from a source beyond the local core's L1 due to a deman…
95 …The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a deman…
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/linux/Documentation/arch/x86/
H A Dtopology.rst91 - On AMD, the Node ID or Core Complex ID containing the Last Level
97 A core consists of 1 or more threads. It does not matter whether the threads
100 AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses
101 "core".
108 AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
122 The cpumask contains all online threads in the core to which a thread
135 The ID of the core to which a thread belongs. It is also printed in /proc/cpuinfo
140 The logical core ID to which a thread belongs.
156 1) CPUID leaf 0x80000026 [Extended CPU Topology] (Core::X86::Cpuid::ExCpuTopology)
159 and provides the topology information of Core, Complex, CCD (Die), and
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