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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp-ax.dtsi13 /delete-property/ dma-coherent;
17 /delete-property/ dma-coherent;
21 /delete-property/ dma-coherent;
25 /delete-property/ dma-coherent;
29 /delete-property/ dma-coherent;
33 /delete-property/ dma-coherent;
37 /delete-property/ dma-coherent;
41 /delete-property/ dma-coherent;
45 /delete-property/ dma-coherent;
49 /delete-property/ dma-coherent;
[all …]
H A Dbcm-nsp.dtsi219 dma-coherent;
229 dma-coherent;
239 dma-coherent;
249 dma-coherent;
259 dma-coherent;
270 dma-coherent;
323 dma-coherent;
331 dma-coherent;
339 dma-coherent;
475 dma-coherent;
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Ddata-fabric.json4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Duncore-interconnect.json12 …n till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.…
21 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
31 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in Dir…
36 …"PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in Dire…
41 … "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
50 … "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
55 … "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A Duncore-interconnect.json12 "BriefDescription": "Each cycle counts number of any coherent requests at memory controller that were issued by any core.",
22 "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
32 "BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches.",
42 "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic.",
52 "BriefDescription": "Each cycle counts number of valid coherent Data Read entries. Such entry is defined as valid when it is allocated until deallocation. Does not include prefetches.",
62 "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
71 "BriefDescription": "Counts number of all coherent Data Read entries. Does not include prefetches.",
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A Duncore-interconnect.json12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …d from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A Duncore-interconnect.json12 …"BriefDescription": "Each cycle counts number of any coherent request at memory controller that we…
22 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
54 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …d from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.…
83 …"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is…
93 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
102 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A Duncore-interconnect.json3 …. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access…
8 …. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access…
22 …n till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.…
31 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
41 … "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Duncore-interconnect.json21 …ing for data returning from the memory controller. Accounts for coherent and non-coherent requests…
30 …are waiting for data return from memory controller. Account for coherent and non-coherent requests…
40 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
50 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Duncore-interconnect.json21 …ing for data returning from the memory controller. Accounts for coherent and non-coherent requests…
30 …are waiting for data return from memory controller. Account for coherent and non-coherent requests…
40 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
50 …"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores,…
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Duncore-interconnect.json12 "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
22 "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
54 "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
64 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
74 "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
83 "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
93 "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
102 "BriefDescription": "Number of all coherent Dat
[all...]
/linux/arch/riscv/mm/
H A Ddma-noncoherent.c3 * RISC-V specific functions to support DMA for non-coherent devices
131 void arch_setup_dma_ops(struct device *dev, bool coherent) in arch_setup_dma_ops() argument
133 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, in arch_setup_dma_ops()
139 WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC, in arch_setup_dma_ops()
140 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
143 dev->dma_coherent = coherent; in arch_setup_dma_ops()
149 "Non-coherent DMA support enabled without a block size\n"); in riscv_noncoherent_supported()
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dicm.c79 void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent) in mlx4_free_icm() argument
87 if (coherent) in mlx4_free_icm()
133 gfp_t gfp_mask, int coherent) in mlx4_alloc_icm() argument
141 /* We use sg_set_buf for coherent allocs, which assumes low memory */ in mlx4_alloc_icm()
142 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM)); in mlx4_alloc_icm()
172 chunk->coherent = coherent; in mlx4_alloc_icm()
174 if (!coherent) in mlx4_alloc_icm()
186 if (coherent) in mlx4_alloc_icm()
204 if (coherent) in mlx4_alloc_icm()
221 if (!coherent && chunk) { in mlx4_alloc_icm()
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Duncore-interconnect.json12 …ts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.…
21 … is waiting for data return from memory controller. Account for coherent and non-coherent requests…
49 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
58 …"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose da…
/linux/drivers/ras/amd/atl/
H A Dinternal.h28 /* Maximum possible number of Coherent Stations within a single Data Fabric. */
148 * These masks operate on the 16-bit Coherent Station IDs,
158 * system-wide Coherent Station Fabric ID.
165 * to the Coherent Station Fabric ID.
172 * to the Coherent Station Fabric ID.
176 /* Number of DRAM Address maps visible in a Coherent Station. */
204 * Logical to Physical Coherent Station Remapping array
206 * Index: Logical Coherent Station Instance ID
207 * Value: Physical Coherent Station Instance ID
256 * Coherent Station Instance ID
[all …]
/linux/arch/arm/mm/
H A Ddma-mapping-nommu.c36 void arch_setup_dma_ops(struct device *dev, bool coherent) in arch_setup_dma_ops() argument
41 * coherent if no cache has been detected. Note that it is not in arch_setup_dma_ops()
45 dev->dma_coherent = cacheid ? coherent : true; in arch_setup_dma_ops()
48 * Assume coherent DMA in case MMU/MPU has not been set up. in arch_setup_dma_ops()
50 dev->dma_coherent = (get_cr() & CR_M) ? coherent : true; in arch_setup_dma_ops()
/linux/arch/arc/plat-hsdk/
H A Dplatform.c88 static int __init hsdk_tweak_node_coherency(const char *path, bool coherent) in hsdk_tweak_node_coherency() argument
99 prop = fdt_getprop(fdt, node, "dma-coherent", &ret); in hsdk_tweak_node_coherency()
106 /* need to remove "dma-coherent" property */ in hsdk_tweak_node_coherency()
107 if (dt_coh_set && !coherent) in hsdk_tweak_node_coherency()
108 ret = fdt_delprop(fdt, node, "dma-coherent"); in hsdk_tweak_node_coherency()
110 /* need to set "dma-coherent" property */ in hsdk_tweak_node_coherency()
111 if (!dt_coh_set && coherent) in hsdk_tweak_node_coherency()
112 ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0); in hsdk_tweak_node_coherency()
120 pr_err("failed to tweak %s to %scoherent\n", path, coherent ? "" : "non"); in hsdk_tweak_node_coherency()
191 bool coherent = !!arc_hsdk_axi_dmac_coherent; in hsdk_init_memory_bridge_axi_dmac() local
[all …]
/linux/kernel/dma/
H A Dcoherent.c3 * Coherent per-device memory handling.
102 * is asked for coherent memory for this device. This shall only be used
160 * Memory was found in the coherent area. in __dma_alloc_from_coherent()
174 * dma_alloc_from_dev_coherent() - allocate memory from device coherent pool
182 * to support allocation from per-device coherent memory pools.
216 * dma_release_from_dev_coherent() - free memory to device coherent memory pool
222 * coherent memory pool and if so, releases that memory.
257 * dma_mmap_from_dev_coherent() - mmap memory from the device coherent pool
265 * coherent memory pool and if so, maps that memory to the provided vma.
267 * Returns 1 if @vaddr belongs to the device coherent pool and the caller
[all …]
/linux/arch/arc/mm/
H A Ddma.c12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
93 void arch_setup_dma_ops(struct device *dev, bool coherent) in arch_setup_dma_ops() argument
100 if (is_isa_arcv2() && ioc_enable && coherent) in arch_setup_dma_ops()
/linux/arch/arc/boot/dts/
H A Daxc003.dtsi94 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
97 * only AXS103 board has HW-coherent DMA peripherals)
98 * We don't need to mark pgu@17000 as dma-coherent because it uses
103 dma-coherent;
107 dma-coherent;
111 dma-coherent;
115 dma-coherent;
H A Daxc003_idu.dtsi101 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
104 * only AXS103 board has HW-coherent DMA peripherals)
105 * We don't need to mark pgu@17000 as dma-coherent because it uses
110 dma-coherent;
114 dma-coherent;
118 dma-coherent;
122 dma-coherent;
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Duncore-interconnect.json3 …"BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory…
22 "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
58 …: "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.…
/linux/drivers/infiniband/hw/mthca/
H A Dmthca_memfree.c88 void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent) in mthca_free_icm() argument
96 if (coherent) in mthca_free_icm()
138 gfp_t gfp_mask, int coherent) in mthca_alloc_icm() argument
145 /* We use sg_set_buf for coherent allocs, which assumes low memory */ in mthca_alloc_icm()
146 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM)); in mthca_alloc_icm()
173 if (coherent) in mthca_alloc_icm()
184 if (coherent) in mthca_alloc_icm()
207 if (!coherent && chunk) { in mthca_alloc_icm()
218 mthca_free_icm(dev, icm, coherent); in mthca_alloc_icm()
236 __GFP_NOWARN, table->coherent); in mthca_table_get()
[all …]
/linux/arch/mips/mm/
H A Ddma-noncoherent.c20 * Warning on the terminology - Linux calls an uncached area coherent; MIPS
21 * terminology calls memory areas with hardware maintained coherency coherent.
24 * However this function is only called on non-I/O-coherent systems and only the
140 void arch_setup_dma_ops(struct device *dev, bool coherent) in arch_setup_dma_ops() argument
142 dev->dma_coherent = coherent; in arch_setup_dma_ops()
/linux/drivers/cpuidle/
H A Dcpuidle-cps.c16 STATE_WAIT = 0, /* MIPS wait instruction, coherent */
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
79 .desc = "non-coherent MIPS wait",
133 pr_cont("coherent wait\n"); in cps_cpuidle_init()
136 pr_cont("non-coherent wait\n"); in cps_cpuidle_init()

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