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Searched full:clock1 (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/mmc/
H A Drenesas,sdhi.yaml133 - description: IMCLK, SDHI channel main clock1.
135 4 times that of SDHI channel main clock1.
/linux/Documentation/devicetree/bindings/ata/
H A Dsnps,dwc-ahci.yaml62 clocks = <&clock1>, <&clock2>;
/linux/drivers/clk/x86/
H A Dclk-fch.c19 /* Auxiliary clock1 enable bit */
/linux/Documentation/devicetree/bindings/regulator/
H A Dfixed-regulator.yaml142 clocks = <&clock1>;
/linux/Documentation/devicetree/bindings/clock/
H A Didt,versaclock5.yaml107 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
/linux/sound/soc/codecs/
H A Dwm8903.c1457 u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1); in wm8903_hw_params() local
1478 clock1 &= ~WM8903_SAMPLE_RATE_MASK; in wm8903_hw_params()
1479 clock1 |= sample_rates[dsp_config].value; in wm8903_hw_params()
1533 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | in wm8903_hw_params()
1535 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; in wm8903_hw_params()
1536 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; in wm8903_hw_params()
1574 snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1); in wm8903_hw_params()
H A Dwm8904.c1303 unsigned int clock1 = 0; in wm8904_hw_params() local
1355 clock1 |= (clk_sys_rates[best].clk_sys_rate in wm8904_hw_params()
1371 clock1 |= (sample_rates[best].sample_rate in wm8904_hw_params()
1411 WM8904_CLK_SYS_RATE_MASK, clock1); in wm8904_hw_params()
/linux/drivers/gpu/drm/
H A Ddrm_edid.c4313 unsigned int clock1, clock2; in drm_match_cea_mode_clock_tolerance() local
4318 clock1 = cea_mode.clock; in drm_match_cea_mode_clock_tolerance()
4321 if (abs(to_match->clock - clock1) > clock_tolerance && in drm_match_cea_mode_clock_tolerance()
4354 unsigned int clock1, clock2; in drm_match_cea_mode() local
4359 clock1 = cea_mode.clock; in drm_match_cea_mode()
4362 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && in drm_match_cea_mode()
4420 unsigned int clock1, clock2; in drm_match_hdmi_mode_clock_tolerance() local
4423 clock1 = hdmi_mode->clock; in drm_match_hdmi_mode_clock_tolerance()
4426 if (abs(to_match->clock - clock1) > clock_tolerance && in drm_match_hdmi_mode_clock_tolerance()
4458 unsigned int clock1, clock2; in drm_match_hdmi_mode() local
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.h484 bool intel_fuzzy_clock_check(int clock1, int clock2);
H A Dintel_display.c4820 bool intel_fuzzy_clock_check(int clock1, int clock2) in intel_fuzzy_clock_check() argument
4824 if (clock1 == clock2) in intel_fuzzy_clock_check()
4827 if (!clock1 || !clock2) in intel_fuzzy_clock_check()
4830 diff = abs(clock1 - clock2); in intel_fuzzy_clock_check()
4832 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) in intel_fuzzy_clock_check()
/linux/sound/ppc/
H A Dsnd_ps3_reg.h367 Sets the divide ration of Master Clock1 (clock output from
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dphy.c2660 /* enable ad/da clock1 for dual-phy reg0x888 */ in rtl92d_update_bbrf_configuration()
2681 /* disable ad/da clock1,0x888 */ in rtl92d_update_bbrf_configuration()
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
H A Dphy.c2950 /* enable ad/da clock1 for dual-phy reg0x888 */ in rtl92du_update_bbrf_configuration()
2967 /* disable ad/da clock1,0x888 */ in rtl92du_update_bbrf_configuration()