Searched full:clock1 (Results 1 – 7 of 7) sorted by relevance
159 - description: IMCLK, SDHI channel main clock1.161 4 times that of SDHI channel main clock1.
62 clocks = <&clock1>, <&clock2>;
19 /* Auxiliary clock1 enable bit */
142 clocks = <&clock1>;
1457 u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1); in wm8903_hw_params() local1478 clock1 &= ~WM8903_SAMPLE_RATE_MASK; in wm8903_hw_params()1479 clock1 |= sample_rates[dsp_config].value; in wm8903_hw_params()1533 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | in wm8903_hw_params()1535 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; in wm8903_hw_params()1536 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; in wm8903_hw_params()1574 snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1); in wm8903_hw_params()
107 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
367 Sets the divide ration of Master Clock1 (clock output from