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/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A D	alpine-v3.dtsi	`28 d-cache-size = <0x8000>; 29 d-cache-line-size = <64>; 30 d-cache-sets = <256>; 31 i-cache-size = <0xc000>; 32 i-cache-line-size = <64>; 33 i-cache-sets = <256>; 34 next-level-cache = <&cluster0_l2>; 42 d-cache-size = <0x8000>; 43 d-cache-line-size = <64>; 44 d-cache [all...]`
/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A D	amd-seattle-cpus.dtsi	`49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <256>; 55 l2-cache = <&L2_0>; 65 i-cache-size = <0xC000>; 66 i-cache-line-size = <64>; 67 i-cache-sets = <256>; [all …]`
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A D	l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4 The cache bindings explained below are Devicetree Specification compliant 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" 15 "fsl,mpc8540-l2-cache-controller" [all …]`
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A D	freescale-l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4 The cache bindings explained below are Devicetree Specification compliant 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" 15 "fsl,mpc8540-l2-cache-controller" [all …]`
H A D	socionext,uniphier-system-cache.yaml	4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 19 const: socionext,uniphier-system-cache 29 Interrupts can be used to notify the completion of cache operations. 35 cache-unified: true 37 cache-size: true 39 cache-sets: true [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	extended.json	6 … cache where the line was originally in a Read-Only state in the cache but has been updated to be … 36 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t… 54 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L… 90 …"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is… 96 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 102 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 108 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 114 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 120 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 126 …ctory write to the Level-1 Data cache directory where the returned cache line was sourced from an … [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	cache.json	111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which… 114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which… 117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami… [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A D	extended.json	6 … cache where the line was originally in a Read-Only state in the cache but has been updated to be … 12 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache" 18 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th… 36 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t… 42 …n into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache" 48 …equest made by the instruction cache. Incremented by one for every TLB2 miss in progress for the L… 54 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L… 90 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is… 96 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 102 …licDescription": "A directory write to the Level-1 Data cache directory where the returned cache l… [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/socionext/
H A D	socionext,uniphier-system-cache.yaml	4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 19 const: socionext,uniphier-system-cache 29 Interrupts can be used to notify the completion of cache operations. 35 cache-unified: true 37 cache-size: true 39 cache-sets: true [all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A D	k3-am654.dtsi	`41 i-cache-size = <0x8000>; 42 i-cache-line-size = <64>; 43 i-cache-sets = <256>; 44 d-cache-size = <0x8000>; 45 d-cache-line-size = <64>; 46 d-cache-sets = <128>; 47 next-level-cache = <&L2_0>; 55 i-cache-size = <0x8000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <256>; [all …]`
H A D	k3-j784s4.dtsi	`70 i-cache-size = <0xc000>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <256>; 73 d-cache-size = <0x8000>; 74 d-cache-line-size = <64>; 75 d-cache-sets = <256>; 76 next-level-cache = <&L2_0>; 84 i-cache-size = <0xc000>; 85 i-cache-line-size = <64>; 86 i-cache [all...]`
H A D	k3-am62a7.dtsi	`44 i-cache-size = <0x8000>; 45 i-cache-line-size = <64>; 46 i-cache-sets = <256>; 47 d-cache-size = <0x8000>; 48 d-cache-line-size = <64>; 49 d-cache-sets = <128>; 50 next-level-cache = <&L2_0>; 58 i-cache-size = <0x8000>; 59 i-cache-line-size = <64>; 60 i-cache-sets = <256>; [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	18 …ory write to the Level-1 Data cache directory where the returned cache line was sourced from the L… 24 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L… 30 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t… 42 …to the Level-1 Data cache where the installed cache line was sourced from memory that is attached … 48 …el-1 Instruction cache where the installed cache line was sourced from memory that is attached to … 54 …-Cache where the line was originally in a Read-Only state in the cache but has been updated to be … 90 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… 96 …y write to the Level-1 Data cache directory where the returned cache line was sourced from an Off … 102 …ctory write to the Level-1 Data cache directory where the returned cache line was sourced from an … 108 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A D	cache.json	102 …cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event… 105 …cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event… 108 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that… 111 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that… 114 …2 cache write streaming mode. This event counts for each cycle where the core is in write streamin… 117 …2 cache write streaming mode. This event counts for each cycle where the core is in write streamin… 120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr… 123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry… 126 …cache write streaming mode. This event counts for each cycle where the core is in write streaming … 129 …cache write streaming mode. This event counts for each cycle where the core is in write streaming … [all …]
/freebsd/contrib/libarchive/libarchive/
H A D	archive_read_disk_set_standard_lookup.c	71 } cache[name_cache_size]; 82 * a simple cache to accelerate such lookups---into the archive_read_disk 101 "Can't allocate uname/gname lookup cache"); in archive_read_disk_set_standard_lookup() 123 struct name_cache cache = (struct name_cache )data; in cleanup() 126 if (cache != NULL) { in cleanup() 127 for (i = 0; i < cache->size; i++) { in cleanup() 128 if (cache->cache[i].name != NULL && in cleanup() 129 cache->cache[ in cleanup() 72 } cache[name_cache_size]; global() member 124 struct name_cache cache = (struct name_cache )data; cleanup() local 142 lookup_name(struct name_cache * cache,const char * (* lookup_fn)(struct name_cache ,id_t),id_t id) lookup_name() argument 187 lookup_uname_helper(struct name_cache cache,id_t id) lookup_uname_helper() argument 232 lookup_uname_helper(struct name_cache * cache,id_t id) lookup_uname_helper() argument 256 lookup_gname_helper(struct name_cache * cache,id_t id) lookup_gname_helper() argument 299 lookup_gname_helper(struct name_cache * cache,id_t id) lookup_gname_helper() argument [all...]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 108 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 111 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 114 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 117 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi… 120 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi… 123 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 126 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each … 132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e… [all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A D	armada-ap806-quad.dtsi	`25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; 27 i-cache-sets = <256>; 28 d-cache-size = <0x8000>; 29 d-cache-line-size = <64>; 30 d-cache-sets = <256>; 31 next-level-cache = <&l2_0>; 40 i-cache-size = <0xc000>; 41 i-cache-line-size = <64>; 42 i-cache-sets = <256>; [all …]`
H A D	armada-ap807-quad.dtsi	`25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; 27 i-cache-sets = <256>; 28 d-cache-size = <0x8000>; 29 d-cache-line-size = <64>; 30 d-cache-sets = <256>; 31 next-level-cache = <&l2_0>; 40 i-cache-size = <0xc000>; 41 i-cache-line-size = <64>; 42 i-cache-sets = <256>; [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	cache.json	12 "BriefDescription": "L1 Cache evictions for dirty data", 17 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache … 27 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem… 41 "BriefDescription": "L2 cache request misses", 46 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 51 "BriefDescription": "L2 cache requests", 56 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", 68 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… 80 …cache line containing the data was in the modified state of another core or modules cache (HITM). … 85 "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A D	extended.json	6 …"A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from… 12 …"A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from… 30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache" 36 …irectory write to the Level-1 D-Cache directory where the returned cache line was sourced from an … 42 …directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an… 48 …directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an… 54 …-Cache where the line was originally in a Read-Only state in the cache but has been updated to be … 60 …irectory write to the Level-1 D-Cache directory where the returned cache line was sourced from an … 66 …irectory write to the Level-1 I-Cache directory where the returned cache line was sourced from an … 78 …te to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached … [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A D	extended.json	6 …directory write to the Level-1 I-Cache directory where the returned cache line was sourced from th… 12 …irectory write to the Level-1 D-Cache directory where the installed cache line was sourced from th… 18 … I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on th… 24 …l-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is o… 30 …-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on th… 36 …-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not o… 42 … the Level-1 D-Cache directory where the installed cache line was sourced from memory that is atta… 48 …o the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to t… 54 …-Cache where the line was originally in a Read-Only state in the cache but has been updated to be … 60 …"PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the s… [all …]
/freebsd/sys/powerpc/mpc85xx/
H A D	mpc85xx_cache.c	`55 {"fsl,8540-l2-cache-controller", 1}, 56 {"fsl,8541-l2-cache-controller", 1}, 57 {"fsl,8544-l2-cache-controller", 1}, 58 {"fsl,8548-l2-cache-controller", 1}, 59 {"fsl,8555-l2-cache-controller", 1}, 60 {"fsl,8568-l2-cache-controller", 1}, 61 {"fsl,b4420-l2-cache-controller", 1}, 62 {"fsl,b4860-l2-cache-controller", 1}, 63 {"fsl,bsc9131-l2-cache-controller", 1}, 64 {"fsl,bsc9132-l2-cache-controller", 1}, [all …]`
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A D	fvp-base-revc.dts	`50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <256>; 56 next-level-cache = <&C0_L2>; 63 i-cache-size = <0x8000>; 64 i-cache-line-size = <64>; 65 i-cache-sets = <256>; [all …]`
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A D	imx8qm.dtsi	`68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 85 i-cache-size = <0x8000>; 86 i-cache-line-size = <64>; 87 i-cache [all...]`
/freebsd/tests/sys/cddl/zfs/tests/cache/
H A D	cache_test.sh	`30 atf_set "descr" "Creating a pool with a cache device succeeds." 37 . $(atf_get_srcdir)/cache.kshlib 38 . $(atf_get_srcdir)/cache.cfg 47 . $(atf_get_srcdir)/cache.kshlib 48 . $(atf_get_srcdir)/cache.cfg 57 atf_set "descr" "Adding a cache device to normal pool works." 64 . $(atf_get_srcdir)/cache.kshlib 65 . $(atf_get_srcdir)/cache.cfg 74 . $(atf_get_srcdir)/cache.kshlib 75 . $(atf_get_srcdir)/cache.cfg [all …]`

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