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Searched full:csr (Results 1 – 25 of 432) sorted by relevance

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/linux/arch/sparc/kernel/
H A Debus.c74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
[all …]
/linux/arch/alpha/kernel/
H A Dcore_tsunami.c181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
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H A Dcore_wildfire.c121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
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H A Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
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H A Derr_ev7.c194 "DM CSR PH", "DM CSR PH", "DM CSR PH",
195 "DM CSR PH", "reserved",
198 "DM CSR PH", "DM CSR PH", "DM CSR PH",
199 "DM CSR PH", "reserved",
202 "DM CSR PH", "DM CSR PH", "DM CSR PH",
203 "DM CSR PH", "reserved",
206 "DM CSR PH", "DM CSR PH", "DM CSR PH",
207 "DM CSR PH", "reserved",
/linux/drivers/usb/musb/
H A Dmusb_gadget.c230 u16 fifo_count = 0, csr; in txstate() local
249 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
255 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
257 musb_ep->end_point.name, csr); in txstate()
261 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
263 musb_ep->end_point.name, csr); in txstate()
269 csr); in txstate()
276 /* setup DMA, then program endpoint CSR */ in txstate()
302 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
304 musb_writew(epio, MUSB_TXCSR, csr in txstate()
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H A Dmusb_cppi41.c56 u16 csr; in save_rx_toggle() local
64 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle()
65 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in save_rx_toggle()
74 u16 csr; in update_rx_toggle() local
83 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in update_rx_toggle()
84 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in update_rx_toggle()
92 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; in update_rx_toggle()
93 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); in update_rx_toggle()
105 u16 csr; in musb_is_tx_fifo_empty() local
108 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty()
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H A Dmusb_host.c91 u16 csr; in musb_h_tx_flush_fifo() local
94 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
95 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
96 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; in musb_h_tx_flush_fifo()
97 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
98 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
115 "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_tx_flush_fifo()
116 ep->epnum, csr)) in musb_h_tx_flush_fifo()
125 u16 csr; in musb_h_ep0_flush_fifo() local
130 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
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H A Dmusbhsdma.c152 u16 csr = 0; in configure_channel() local
158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel()
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel()
178 csr); in configure_channel()
228 u16 csr; in dma_channel_abort() local
239 csr = musb_readw(mbase, offset); in dma_channel_abort()
240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in dma_channel_abort()
241 musb_writew(mbase, offset, csr); in dma_channel_abort()
242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
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/linux/arch/riscv/kvm/
H A Dvcpu.c59 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_context_reset() local
64 memset(csr, 0, sizeof(*csr)); in kvm_riscv_vcpu_context_reset()
357 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_flush_interrupts() local
368 csr->hvip &= ~mask; in kvm_riscv_vcpu_flush_interrupts()
369 csr->hvip |= val; in kvm_riscv_vcpu_flush_interrupts()
383 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_sync_interrupts() local
386 csr->vsie = ncsr_read(CSR_VSIE); in kvm_riscv_vcpu_sync_interrupts()
393 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { in kvm_riscv_vcpu_sync_interrupts()
406 if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { in kvm_riscv_vcpu_sync_interrupts()
576 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_arch_vcpu_load() local
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H A Daia.c53 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts() local
66 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
67 csr->hviph |= val; in kvm_riscv_vcpu_aia_flush_interrupts()
73 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_sync_interrupts() local
78 csr->vsieh = ncsr_read(CSR_VSIEH); in kvm_riscv_vcpu_aia_sync_interrupts()
116 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_aia_update_hvip() local
124 ncsr_write(CSR_HVICTL, aia_hvictl_value(!!(csr->hvip & BIT(IRQ_VS_EXT)))); in kvm_riscv_vcpu_aia_update_hvip()
129 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_load() local
137 nacl_csr_write(nsh, CSR_VSISELECT, csr->vsiselect); in kvm_riscv_vcpu_aia_load()
138 nacl_csr_write(nsh, CSR_HVIPRIO1, csr->hviprio1); in kvm_riscv_vcpu_aia_load()
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/linux/arch/loongarch/include/asm/
H A Dkvm_csr.h14 #define gcsr_read(csr) \ argument
20 : [reg] "i" (csr) \
25 #define gcsr_write(v, csr) \ argument
31 : [reg] "i" (csr) \
36 #define gcsr_xchg(v, m, csr) \ argument
42 : [mask] "r" (m), [reg] "i" (csr) \
182 #define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid)) argument
183 #define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid)) argument
185 #define kvm_read_clear_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_write(0, gid)) argument
189 static __always_inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid) in kvm_read_sw_gcsr() argument
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/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c112 u32 csr; in proc_ep_show() local
119 csr = __raw_readl(ep->creg); in proc_ep_show()
132 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", in proc_ep_show()
133 csr, in proc_ep_show()
134 (csr & 0x07ff0000) >> 16, in proc_ep_show()
135 str_enabled_disabled(csr & (1 << 15)), in proc_ep_show()
136 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
137 types[(csr & 0x700) >> 8], in proc_ep_show()
140 (!(csr & 0x700)) in proc_ep_show()
141 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
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/linux/arch/sh/kernel/cpu/
H A Dadc.c16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
/linux/arch/alpha/include/asm/
H A Dcore_t2.h206 unsigned long elcmc_bcc; /* CSR 0 */
207 unsigned long elcmc_bcce; /* CSR 1 */
208 unsigned long elcmc_bccea; /* CSR 2 */
209 unsigned long elcmc_bcue; /* CSR 3 */
210 unsigned long elcmc_bcuea; /* CSR 4 */
211 unsigned long elcmc_dter; /* CSR 5 */
212 unsigned long elcmc_cbctl; /* CSR 6 */
213 unsigned long elcmc_cbe; /* CSR 7 */
214 unsigned long elcmc_cbeal; /* CSR 8 */
215 unsigned long elcmc_cbeah; /* CSR 9 */
[all …]
/linux/drivers/watchdog/
H A Dshwdt.c85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
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/linux/include/linux/
H A Drio_regs.h103 #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */
129 #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */
130 #define RIO_DOORBELL_CSR 0x44 /* [II, <= 1.2] Doorbell CSR */
146 #define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
156 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
160 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
161 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
301 #define RIO_EM_LTL_ERR_DETECT 0x008 /* Logical/Transport Layer Error Detect CSR */
302 #define RIO_EM_LTL_ERR_EN 0x00c /* Logical/Transport Layer Error Enable CSR */
307 #define RIO_EM_LTL_HIADDR_CAP 0x010 /* Logical/Transport Layer High Address Capture CSR */
[all …]
/linux/sound/soc/intel/atom/sst/
H A Dsst_loader.c56 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
59 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
61 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
63 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld()
64 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
65 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
67 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
69 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld()
70 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
72 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hal.h125 #define SET_CAP_CSR(handle, csr, val) \ argument
126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \ argument
128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
/linux/arch/mips/dec/
H A Dkn02-irq.c30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
34 *csr = cached_kn02_csr; in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
43 *csr = cached_kn02_csr; in mask_kn02_irq()
53 .name = "KN02-CSR",
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
68 *csr = cached_kn02_csr; in init_kn02_irqs()
/linux/arch/riscv/kernel/
H A Dqos.c14 * Cached value of srmcfg csr for each cpu. Seeded to U32_MAX so the next
15 * __switch_to_srmcfg() unconditionally writes the CSR. The encoding
29 * __switch_to_srmcfg() always writes the CSR.
31 * Ssqosid leaves the CSR implementation-defined across hart stop/start,
35 * task runs and the CSR is written on that task's first switch.
51 * this hook __switch_to_srmcfg() would skip the CSR write when the
61 * The CSR is implementation-defined across the low-power in riscv_srmcfg_pm_notify()
63 * CSR for the current task so it does not run mis-tagged in riscv_srmcfg_pm_notify()
/linux/drivers/misc/eeprom/
H A Didt_89hpesx.c27 * <CSR address>:<CSR value>
28 * So reading the content of the file gives current CSR address and it value.
29 * If User-space application wishes to change current CSR address,
31 * $ echo "<CSR address>" > /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>
32 * If it wants to change the CSR value as well, the format of the write
34 * $ echo "<CSR address>:<CSR value>" > \
36 * CSR address and value can be any of hexadecimal, decimal or octal format.
69 * @inicsrcmd: Initial cmd value for CSR read/write operations
72 * @csr: CSR address to perform read operation
92 u16 csr; member
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/linux/drivers/usb/mtu3/
H A Dmtu3_gadget_ep0.c139 u32 csr; in ep0_stall_set() local
142 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_stall_set()
144 csr |= EP0_SENDSTALL | pktrdy; in ep0_stall_set()
146 csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
515 u32 csr; in ep0_rx_state() local
520 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_rx_state()
537 csr |= EP0_RXPKTRDY; in ep0_rx_state()
545 csr |= EP0_DATAEND; in ep0_rx_state()
550 csr |= EP0_RXPKTRDY | EP0_SENDSTALL; in ep0_rx_state()
[all …]
/linux/arch/loongarch/kvm/
H A Dmain.c22 int get_gcsr_flag(int csr) in get_gcsr_flag() argument
24 if (csr < CSR_MAX_NUMS) in get_gcsr_flag()
25 return gcsr_flag[csr]; in get_gcsr_flag()
30 static inline void set_gcsr_sw_flag(int csr) in set_gcsr_sw_flag() argument
32 if (csr < CSR_MAX_NUMS) in set_gcsr_sw_flag()
33 gcsr_flag[csr] |= SW_GCSR; in set_gcsr_sw_flag()
36 static inline void set_gcsr_hw_flag(int csr) in set_gcsr_hw_flag() argument
38 if (csr < CSR_MAX_NUMS) in set_gcsr_hw_flag()
39 gcsr_flag[csr] |= HW_GCSR; in set_gcsr_hw_flag()
43 * The default value of gcsr_flag[CSR] is 0, and we use this
[all …]
/linux/drivers/pcmcia/
H A Dpxa2xx_sharpsl.c57 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
65 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
66 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
74 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
79 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); in sharpsl_pcmcia_socket_state()
90 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
91 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
92 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
93 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
94 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
[all …]

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