| /linux/drivers/crypto/intel/qat/qat_common/ |
| H A D | icp_qat_hw_20_comp.h | 23 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
48 QAT_FIELD_SET(val32, csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
51 QAT_FIELD_SET(val32, csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
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| H A D | icp_qat_hal.h | 125 #define SET_CAP_CSR(handle, csr, val) \ argument
126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \ argument
128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
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| /linux/arch/loongarch/kvm/ |
| H A D | vcpu.c | 73 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_save_guest_pmu() local
75 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR0); in kvm_save_guest_pmu()
76 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR1); in kvm_save_guest_pmu()
77 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR2); in kvm_save_guest_pmu()
78 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR3); in kvm_save_guest_pmu()
79 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0); in kvm_save_guest_pmu()
80 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1); in kvm_save_guest_pmu()
81 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2); in kvm_save_guest_pmu()
82 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); in kvm_save_guest_pmu()
87 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_restore_guest_pmu() local
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| H A D | timer.c | 46 kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_TVAL, 0); in kvm_init_timer()
57 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_restore_timer() local
60 * Set guest stable timer cfg csr in kvm_restore_timer()
61 * Disable timer before restore estat CSR register, avoid to in kvm_restore_timer()
64 cfg = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TCFG); in kvm_restore_timer()
67 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ESTAT); in kvm_restore_timer()
68 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TCFG); in kvm_restore_timer()
71 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TVAL); in kvm_restore_timer()
83 * If oneshot timer is fired, CSR TVAL will be -1, there are two in kvm_restore_timer()
90 ticks = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_TVAL); in kvm_restore_timer()
[all …]
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| /linux/arch/sparc/kernel/ |
| H A D | ebus.c | 74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
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| /linux/arch/alpha/kernel/ |
| H A D | core_tsunami.c | 181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
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| H A D | core_wildfire.c | 121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
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| H A D | core_titan.c | 207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
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| H A D | sys_marvel.c | 96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
174 volatile unsigned long *csr, in io7_redirect_irq() argument
179 val = *csr; in io7_redirect_irq()
183 *csr = val; in io7_redirect_irq()
185 *csr; in io7_redirect_irq()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
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| H A D | err_ev7.c | 194 "DM CSR PH", "DM CSR PH", "DM CSR PH",
195 "DM CSR PH", "reserved",
198 "DM CSR PH", "DM CSR PH", "DM CSR PH",
199 "DM CSR PH", "reserved",
202 "DM CSR PH", "DM CSR PH", "DM CSR PH",
203 "DM CSR PH", "reserved",
206 "DM CSR PH", "DM CSR PH", "DM CSR PH",
207 "DM CSR PH", "reserved",
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| /linux/drivers/usb/musb/ |
| H A D | musb_gadget.c | 230 u16 fifo_count = 0, csr; in txstate() local
249 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
255 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
257 musb_ep->end_point.name, csr); in txstate()
261 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
263 musb_ep->end_point.name, csr); in txstate()
269 csr); in txstate()
276 /* setup DMA, then program endpoint CSR */ in txstate()
302 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
304 musb_writew(epio, MUSB_TXCSR, csr in txstate()
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| H A D | musbhsdma.c | 152 u16 csr = 0; in configure_channel() local
158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel()
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel()
178 csr); in configure_channel()
228 u16 csr; in dma_channel_abort() local
239 csr = musb_readw(mbase, offset); in dma_channel_abort()
240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in dma_channel_abort()
241 musb_writew(mbase, offset, csr); in dma_channel_abort()
242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
[all …]
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| /linux/arch/riscv/kvm/ |
| H A D | aia.c | 50 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts() local
60 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
61 csr->hviph |= val; in kvm_riscv_vcpu_aia_flush_interrupts()
67 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_sync_interrupts() local
70 csr->vsieh = ncsr_read(CSR_VSIEH); in kvm_riscv_vcpu_aia_sync_interrupts()
99 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_aia_update_hvip() local
107 ncsr_write(CSR_HVICTL, aia_hvictl_value(!!(csr->hvip & BIT(IRQ_VS_EXT)))); in kvm_riscv_vcpu_aia_update_hvip()
112 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_load() local
120 nacl_csr_write(nsh, CSR_VSISELECT, csr->vsiselect); in kvm_riscv_vcpu_aia_load()
121 nacl_csr_write(nsh, CSR_HVIPRIO1, csr->hviprio1); in kvm_riscv_vcpu_aia_load()
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| H A D | vcpu.c | 57 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_context_reset() local
62 memset(csr, 0, sizeof(*csr)); in kvm_riscv_vcpu_context_reset()
349 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_flush_interrupts() local
356 csr->hvip &= ~mask; in kvm_riscv_vcpu_flush_interrupts()
357 csr->hvip |= val; in kvm_riscv_vcpu_flush_interrupts()
368 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_sync_interrupts() local
371 csr->vsie = ncsr_read(CSR_VSIE); in kvm_riscv_vcpu_sync_interrupts()
375 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { in kvm_riscv_vcpu_sync_interrupts()
388 if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { in kvm_riscv_vcpu_sync_interrupts()
581 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_arch_vcpu_load() local
[all …]
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| /linux/arch/loongarch/include/asm/ |
| H A D | kvm_csr.h | 14 #define gcsr_read(csr) \ argument
20 : [reg] "i" (csr) \
25 #define gcsr_write(v, csr) \ argument
31 : [reg] "i" (csr) \
36 #define gcsr_xchg(v, m, csr) \ argument
42 : [mask] "r" (m), [reg] "i" (csr) \
182 #define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid)) argument
183 #define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid)) argument
185 #define kvm_read_clear_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_write(0, gid)) argument
189 static __always_inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid) in kvm_read_sw_gcsr() argument
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| /linux/drivers/usb/gadget/udc/ |
| H A D | at91_udc.c | 112 u32 csr; in proc_ep_show() local
119 csr = __raw_readl(ep->creg); in proc_ep_show()
132 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", in proc_ep_show()
133 csr, in proc_ep_show()
134 (csr & 0x07ff0000) >> 16, in proc_ep_show()
135 str_enabled_disabled(csr & (1 << 15)), in proc_ep_show()
136 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
137 types[(csr & 0x700) >> 8], in proc_ep_show()
140 (!(csr & 0x700)) in proc_ep_show()
141 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
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| /linux/arch/alpha/include/asm/ |
| H A D | core_t2.h | 206 unsigned long elcmc_bcc; /* CSR 0 */
207 unsigned long elcmc_bcce; /* CSR 1 */
208 unsigned long elcmc_bccea; /* CSR 2 */
209 unsigned long elcmc_bcue; /* CSR 3 */
210 unsigned long elcmc_bcuea; /* CSR 4 */
211 unsigned long elcmc_dter; /* CSR 5 */
212 unsigned long elcmc_cbctl; /* CSR 6 */
213 unsigned long elcmc_cbe; /* CSR 7 */
214 unsigned long elcmc_cbeal; /* CSR 8 */
215 unsigned long elcmc_cbeah; /* CSR 9 */
[all …]
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| /linux/arch/sh/kernel/cpu/ |
| H A D | adc.c | 16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
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| /linux/include/linux/ |
| H A D | rio_regs.h | 103 #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */
129 #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */
130 #define RIO_DOORBELL_CSR 0x44 /* [II, <= 1.2] Doorbell CSR */
146 #define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
156 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
160 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
161 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
301 #define RIO_EM_LTL_ERR_DETECT 0x008 /* Logical/Transport Layer Error Detect CSR */
302 #define RIO_EM_LTL_ERR_EN 0x00c /* Logical/Transport Layer Error Enable CSR */
307 #define RIO_EM_LTL_HIADDR_CAP 0x010 /* Logical/Transport Layer High Address Capture CSR */
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| /linux/drivers/watchdog/ |
| H A D | shwdt.c | 85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
[all …]
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| /linux/drivers/net/pcs/ |
| H A D | pcs-xpcs-plat.c | 41 static u16 xpcs_mmio_addr_page(ptrdiff_t csr) in xpcs_mmio_addr_page() argument
43 return FIELD_GET(0x1fff00, csr); in xpcs_mmio_addr_page()
46 static ptrdiff_t xpcs_mmio_addr_offset(ptrdiff_t csr) in xpcs_mmio_addr_offset() argument
48 return FIELD_GET(0xff, csr); in xpcs_mmio_addr_offset()
54 ptrdiff_t csr, ofs; in xpcs_mmio_read_reg_indirect() local
58 csr = xpcs_mmio_addr_format(dev, reg); in xpcs_mmio_read_reg_indirect()
59 page = xpcs_mmio_addr_page(csr); in xpcs_mmio_read_reg_indirect()
60 ofs = xpcs_mmio_addr_offset(csr); in xpcs_mmio_read_reg_indirect()
85 ptrdiff_t csr, ofs; in xpcs_mmio_write_reg_indirect() local
89 csr = xpcs_mmio_addr_format(dev, reg); in xpcs_mmio_write_reg_indirect()
[all …]
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| /linux/sound/soc/intel/atom/sst/ |
| H A D | sst_loader.c | 56 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
59 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
61 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
63 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld()
64 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
65 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
67 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
69 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld()
70 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
72 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
[all …]
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| /linux/drivers/dma/ |
| H A D | tegra186-gpc-dma.c | 24 /* CSR register */
189 u32 csr; member
291 dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", in tegra_dma_dump_chan_regs()
457 u32 csr, status; in tegra_dma_disable() local
459 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); in tegra_dma_disable()
462 csr &= ~TEGRA_GPCDMA_CSR_IE_EOC; in tegra_dma_disable()
465 csr &= ~TEGRA_GPCDMA_CSR_ENB; in tegra_dma_disable()
466 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); in tegra_dma_disable()
507 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_configure_next_sg()
539 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
[all …]
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| /linux/arch/mips/dec/ |
| H A D | kn02-irq.c | 30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
34 *csr = cached_kn02_csr; in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
43 *csr = cached_kn02_csr; in mask_kn02_irq()
53 .name = "KN02-CSR",
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
68 *csr = cached_kn02_csr; in init_kn02_irqs()
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| /linux/drivers/misc/eeprom/ |
| H A D | idt_89hpesx.c | 27 * <CSR address>:<CSR value>
28 * So reading the content of the file gives current CSR address and it value.
29 * If User-space application wishes to change current CSR address,
31 * $ echo "<CSR address>" > /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>
32 * If it wants to change the CSR value as well, the format of the write
34 * $ echo "<CSR address>:<CSR value>" > \
36 * CSR address and value can be any of hexadecimal, decimal or octal format.
70 * @inicsrcmd: Initial cmd value for CSR read/write operations
73 * @csr: CSR address to perform read operation
93 u16 csr; member
[all …]
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