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/linux/Documentation/admin-guide/media/
H A Dimx7.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
14 - CMOS Sensor Interface (CSI)
15 - Video Multiplexer
16 - MIPI CSI-2 Receiver
18 .. code-block:: none
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
24 | U | ------> CSI ---> Capture
27 Parallel Camera Input ----------------> | /
34 --------
[all …]
/linux/drivers/staging/media/tegra-video/
H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * VI and CSI SoC specific data, operations and registers accessors.
17 #include "csi.h"
40 /* Tegra210 VI CSI registers */
64 /* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
86 #define CSI_PP_SINGLE_SHOT_ENABLE (0x1 << 2)
92 /* Tegra210 CSI PHY registers */
117 #define PG_MODE_OFFSET 2
150 writel_relaxed(val, chan->vi->iomem + addr); in tegra_vi_write()
155 return readl_relaxed(chan->vi->iomem + addr); in tegra_vi_read()
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H A Dcsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <media/media-entity.h>
10 #include <media/v4l2-async.h>
11 #include <media/v4l2-subdev.h>
14 * Each CSI brick supports max of 4 lanes that can be used as either
15 * one x4 port using both CILA and CILB partitions of a CSI brick or can
19 #define CSI_PORTS_PER_BRICK 2
22 /* Maximum 2 CSI x4 ports can be ganged up for streaming */
23 #define GANG_PORTS_MAX 2
25 /* each CSI channel can have one sink and one source pads */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-inno-csi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
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H A Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
11 - Julien Stephan <jstephan@baylibre.com>
12 - Andy Hsieh <andy.hsieh@mediatek.com>
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
23 - mediatek,mt8365-csi-rx
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/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 CSI controller
10 - Svyatoslav Ryhel <clamor95@gmail.com>
15 - nvidia,tegra20-csi
16 - nvidia,tegra30-csi
24 - description: module clock
25 - description: PAD A clock
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H A Dnvidia,tegra210-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra CSI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^csi@[0-9a-f]+$"
19 - nvidia,tegra210-csi
26 - description: module clock
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/linux/drivers/media/platform/sunxi/sun4i-csi/
H A Dsun4i_v4l2.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2016-2019 Bootlin
12 #include <media/v4l2-ioctl.h>
13 #include <media/v4l2-mc.h>
14 #include <media/videobuf2-v4l2.h>
30 .hsub = 2,
31 .vsub = 2,
56 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); in sun4i_csi_querycap()
57 strscpy(cap->card, "sun4i-csi", sizeof(cap->card)); in sun4i_csi_querycap()
65 if (inp->index != 0) in sun4i_csi_enum_input()
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/linux/Documentation/devicetree/bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
22 csi@3,0 {
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-generic.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
9 Generic line-based metadata formats
15 These generic line-based metadata formats define the memory layout of the data
18 .. _v4l2-meta-fmt-generic-8:
21 -----------------------
23 The V4L2_META_FMT_GENERIC_8 format is a plain 8-bit metadata format. This format
24 is used on CSI-2 for 8 bits per :term:`Data Unit`.
27 packed into one 16-bit Data Unit. Otherwise the 16 bits per pixel dataformat is
28 :ref:`V4L2_META_FMT_GENERIC_CSI2_16 <v4l2-meta-fmt-generic-csi2-16>`.
35 .. flat-table:: Sample 4x2 Metadata Frame
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/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx7-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)
10 - Rui Miguel Silva <rmfrfs@gmail.com>
13 This is device node for the CMOS Sensor Interface (CSI) which enables the
19 - enum:
20 - fsl,imx8mq-csi
21 - fsl,imx7-csi
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H A Dti,omap3isp.txt4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
14 CSI PHYs and receivers registers.
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
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H A Dallwinner,sun6i-a31-csi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 CMOS Sensor Interface (CSI)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
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H A Dallwinner,sun4i-a10-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 CMOS Sensor Interface (CSI)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
13 description: |-
20 - const: allwinner,sun4i-a10-csi1
21 - const: allwinner,sun7i-a20-csi0
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/linux/drivers/media/platform/nxp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 tristate "NXP CSI Bridge driver"
17 Driver for the NXP Camera Sensor Interface (CSI) Bridge. This device
21 tristate "NXP i.MX8MQ MIPI CSI-2 receiver"
28 Video4Linux2 driver for the MIPI CSI-2 receiver found on the i.MX8MQ
32 tristate "NXP MIPI CSI-2 CSIS receiver found on i.MX7 and i.MX8 models"
39 Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
42 source "drivers/media/platform/nxp/imx8-isi/Kconfig"
53 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
57 tristate "NXP MX2 eMMa-PrP support"
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/linux/include/video/
H A Dimx-ipu-v3.h2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
8 * http://www.opensource.org/licenses/lgpl-license.html
21 #include <media/v4l2-mediabus.h>
56 * Enumeration of CSI destinations
69 #define IPU_ROT_BIT_90 (1 << 2)
83 /* 90-degree rotations require the IRT unit */
116 #define IPUV3_CHANNEL_CSI2 2
121 * but the direct CSI->VDI linking is handled the same way as IDMAC
123 * these channel names are used to support the direct CSI
495 int csi; global() member
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/linux/arch/arm64/boot/dts/renesas/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb
3 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
4 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
5 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
6 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb
7 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
8 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
9 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
11 dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
[all …]
/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-csi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - CSI-2 Receiver
16 #include <linux/phy/phy-mipi-dphy.h>
18 #include <media/v4l2-ctrl
37 struct rkisp1_csi *csi = &rkisp1->csi; rkisp1_csi_link_sensor() local
61 rkisp1_csi_config(struct rkisp1_csi * csi,const struct rkisp1_sensor_async * sensor,const struct rkisp1_mbus_info * format) rkisp1_csi_config() argument
113 rkisp1_csi_enable(struct rkisp1_csi * csi) rkisp1_csi_enable() argument
123 rkisp1_csi_disable(struct rkisp1_csi * csi) rkisp1_csi_disable() argument
149 rkisp1_csi_start(struct rkisp1_csi * csi,const struct rkisp1_sensor_async * sensor,const struct rkisp1_mbus_info * format) rkisp1_csi_start() argument
186 rkisp1_csi_stop(struct rkisp1_csi * csi) rkisp1_csi_stop() argument
310 struct rkisp1_csi *csi = to_rkisp1_csi(sd); rkisp1_csi_set_fmt() local
350 struct rkisp1_csi *csi = to_rkisp1_csi(sd); rkisp1_csi_s_stream() local
439 struct rkisp1_csi *csi = &rkisp1->csi; rkisp1_csi_register() local
487 struct rkisp1_csi *csi = &rkisp1->csi; rkisp1_csi_unregister() local
499 struct rkisp1_csi *csi = &rkisp1->csi; rkisp1_csi_init() local
515 struct rkisp1_csi *csi = &rkisp1->csi; rkisp1_csi_cleanup() local
[all...]
/linux/drivers/media/pci/intel/ivsc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
15 Context Engine) and CSI (Camera Serial Interface), each of which
17 of the sensor between the IVSC and the host CPU while the CSI is
19 sensor transmits over the CSI-2 bus between the IVSC and the
20 host CPU and to configure the CSI-2 bus itself.
22 The modules will be called ivsc-ace and ivsc-csi.
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
[all …]
/linux/arch/powerpc/boot/dts/
H A Do2d.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 gpio-controller;
13 fsl,has-wdt;
14 fsl,wdt-on-boot = <0>;
16 &gpt1 { gpio-controller; };
33 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cell-index = <0>;
48 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun8i-v3s.c6 * Based on pinctrl-sun8i-h3.c, which is:
9 * Based on pinctrl-sun8i-a23.c, which is:
10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
14 * License version 2. This program is licensed "as is" without any
23 #include "pinctrl-sunxi.h"
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
44 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
175 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2),
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,rzv2m-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 - $ref: spi-controller.yaml#
18 const: renesas,rzv2m-csi
28 - description: The clock used to generate the output clock (CSICLK)
[all …]

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