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/linux/drivers/gpu/drm/i915/gt/
H A Dgen8_engine_cs.c16 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
58 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
59 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
60 return PTR_ERR(cs); in gen8_emit_flush_rcs()
63 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
69 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); in gen8_emit_flush_rcs()
72 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); in gen8_emit_flush_rcs()
74 intel_ring_advance(rq, cs); in gen8_emit_flush_rcs()
81 u32 cmd, *cs; in gen8_emit_flush_xcs() local
[all …]
H A Dgen6_engine_cs.c32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
60 u32 *cs; in gen6_emit_post_sync_nonzero_flush() local
62 cs = intel_ring_begin(rq, 6); in gen6_emit_post_sync_nonzero_flush()
63 if (IS_ERR(cs)) in gen6_emit_post_sync_nonzero_flush()
64 return PTR_ERR(cs); in gen6_emit_post_sync_nonzero_flush()
66 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
67 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen6_emit_post_sync_nonzero_flush()
68 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_post_sync_nonzero_flush()
69 *cs++ = 0; /* low dword */ in gen6_emit_post_sync_nonzero_flush()
70 *cs++ = 0; /* high dword */ in gen6_emit_post_sync_nonzero_flush()
[all …]
H A Dgen8_engine_cs.h43 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
44 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
46 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
47 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
48 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
50 u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);
79 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) in __gen8_emit_write_rcs() argument
81 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
82 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE; in __gen8_emit_write_rcs()
83 *cs++ = offset; in __gen8_emit_write_rcs()
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H A Dselftest_engine_pm.c34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
49 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_store()
50 *cs++ = offset; in emit_store()
51 *cs++ = 0; in emit_store()
[all …]
/linux/kernel/time/
H A Dclocksource.c23 static void clocksource_enqueue(struct clocksource *cs);
25 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
27 u64 delta = clocksource_delta(end, start, cs->mask, cs->max_raw_delta); in cycles_to_nsec_safe()
29 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
30 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
32 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
125 * a lower bound for cs->uncertainty_margin values when registering clocks.
144 * Default for maximum permissible skew when cs->uncertainty_margin is
145 * not specified, and the lower bound even when cs->uncertainty_margin
147 * clocks with unspecified cs->uncertainty_margin, so this macro is used
[all …]
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c23 static u32 *pxp_emit_session_selection(u32 *cs, u32 idx) in pxp_emit_session_selection() argument
25 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
28 *cs++ = MI_FLUSH_DW; in pxp_emit_session_selection()
29 *cs++ = 0; in pxp_emit_session_selection()
30 *cs++ = 0; in pxp_emit_session_selection()
33 *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx); in pxp_emit_session_selection()
35 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
38 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN | in pxp_emit_session_selection()
40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
41 *cs++ = 0; in pxp_emit_session_selection()
[all …]
/linux/kernel/cgroup/
H A Dcpuset.c146 struct cpuset *cs = task_cs(p); in inc_dl_tasks_cs() local
148 cs->nr_deadline_tasks++; in inc_dl_tasks_cs()
153 struct cpuset *cs = task_cs(p); in dec_dl_tasks_cs() local
155 cs->nr_deadline_tasks--; in dec_dl_tasks_cs()
158 static inline bool is_partition_valid(const struct cpuset *cs) in is_partition_valid() argument
160 return cs->partition_root_state > 0; in is_partition_valid()
163 static inline bool is_partition_invalid(const struct cpuset *cs) in is_partition_invalid() argument
165 return cs->partition_root_state < 0; in is_partition_invalid()
168 static inline bool cs_is_member(const struct cpuset *cs) in cs_is_member() argument
170 return cs->partition_root_state == PRS_MEMBER; in cs_is_member()
[all …]
H A Dcpuset-v1.c11 struct cpuset *cs; member
148 static int update_relax_domain_level(struct cpuset *cs, s64 val) in update_relax_domain_level() argument
155 if (val != cs->relax_domain_level) { in update_relax_domain_level()
156 cs->relax_domain_level = val; in update_relax_domain_level()
157 if (!cpumask_empty(cs->cpus_allowed) && in update_relax_domain_level()
158 is_sched_load_balance(cs)) in update_relax_domain_level()
168 struct cpuset *cs = css_cs(css); in cpuset_write_s64() local
173 if (!is_cpuset_online(cs)) in cpuset_write_s64()
179 retval = update_relax_domain_level(cs, val); in cpuset_write_s64()
192 struct cpuset *cs = css_cs(css); in cpuset_read_s64() local
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H A Dcpuset-internal.h196 static inline struct cpuset *parent_cs(struct cpuset *cs) in parent_cs() argument
198 return css_cs(cs->css.parent); in parent_cs()
202 static inline bool is_cpuset_online(struct cpuset *cs) in is_cpuset_online() argument
204 return css_is_online(&cs->css) && !css_is_dying(&cs->css); in is_cpuset_online()
207 static inline int is_cpu_exclusive(const struct cpuset *cs) in is_cpu_exclusive() argument
209 return test_bit(CS_CPU_EXCLUSIVE, &cs->flags); in is_cpu_exclusive()
212 static inline int is_mem_exclusive(const struct cpuset *cs) in is_mem_exclusive() argument
214 return test_bit(CS_MEM_EXCLUSIVE, &cs->flags); in is_mem_exclusive()
217 static inline int is_mem_hardwall(const struct cpuset *cs) in is_mem_hardwall() argument
219 return test_bit(CS_MEM_HARDWALL, &cs->flags); in is_mem_hardwall()
[all …]
/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c234 const struct stm32_fmc2_prop *prop, int cs);
235 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
238 int cs, u32 setup);
243 int cs) in stm32_fmc2_ebi_check_mux() argument
248 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
260 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
265 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
277 int cs) in stm32_fmc2_ebi_check_sync_trans() argument
282 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
294 int cs) in stm32_fmc2_ebi_mp25_check_cclk() argument
[all …]
H A Domap-gpmc.c207 /* Structure to save gpmc cs context */
278 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
282 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
286 static u32 gpmc_cs_read_reg(int cs, int idx) in gpmc_cs_read_reg() argument
290 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_read_reg()
307 * @cs: Chip Select Region.
310 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
313 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) in gpmc_get_clk_period() argument
322 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); in gpmc_get_clk_period()
335 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, in gpmc_ns_to_clk_ticks() argument
[all …]
/linux/sound/core/
H A Dpcm_iec958.c14 * @cs: channel status buffer, at least four bytes
17 * Create the consumer format channel status data in @cs of maximum size
29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
38 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; in snd_pcm_create_iec958_consumer_default()
39 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; in snd_pcm_create_iec958_consumer_default()
42 cs[4] = IEC958_AES4_CON_WORDLEN_NOTID; in snd_pcm_create_iec958_consumer_default()
49 u8 *cs, size_t len) in fill_iec958_consumer() argument
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt34 - CS-specific partition/range. If continuous, must be
38 - control partition which is common for all CS
56 Child chip-select (cs) nodes contain the memory devices nodes connected to
60 Required child cs node properties:
73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
79 Optional child cs node properties:
81 - ti,cs-bus-width: width of the asynchronous device's data bus
84 - ti,cs-select-strobe-mode: enable/disable select strobe mode
89 - ti,cs-extended-wait-mode: enable/disable extended wait mode
95 - ti,cs-min-turnaround-ns: minimum turn around time, ns
[all …]
H A Dst,stm32-fmc2-ebi-props.yaml14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
40 st,fmc2-ebi-cs-mux-enable:
46 st,fmc2-ebi-cs-buswidth:
52 st,fmc2-ebi-cs-waitpol-high:
57 st,fmc2-ebi-cs-waitcfg-enable:
64 st,fmc2-ebi-cs-wait-enable:
70 st,fmc2-ebi-cs-asyncwait-enable:
76 st,fmc2-ebi-cs-cpsize:
84 st,fmc2-ebi-cs-byte-lane-setup-ns:
[all …]
/linux/arch/m68k/include/asm/
H A Dm5307sim.h51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
60 #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
61 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
[all …]
/linux/drivers/accel/habanalabs/common/
H A Dhw_queue.c41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_hw_queue_update_ci()
58 * 1. All queues of a non completion CS will never get a completion. in hl_hw_queue_update_ci()
62 if (!cs_needs_completion(cs) || q->queue_type == QUEUE_TYPE_INT) in hl_hw_queue_update_ci()
63 atomic_add(cs->jobs_in_queue_cnt[i], &q->ci); in hl_hw_queue_update_ci()
208 * more than once per CS for the same queue
281 struct hl_device *hdev = job->cs->ctx->hdev; in ext_queue_schedule_job()
301 /* Skip completion flow in case this is a non completion CS */ in ext_queue_schedule_job()
302 if (!cs_needs_completion(job->cs)) in ext_queue_schedule_job()
346 struct hl_device *hdev = job->cs->ctx->hdev; in int_queue_schedule_job()
[all …]
/linux/fs/fuse/
H A Ddev.c840 void fuse_copy_init(struct fuse_copy_state *cs, bool write, in fuse_copy_init() argument
843 memset(cs, 0, sizeof(*cs)); in fuse_copy_init()
844 cs->write = write; in fuse_copy_init()
845 cs->iter = iter; in fuse_copy_init()
849 static void fuse_copy_finish(struct fuse_copy_state *cs) in fuse_copy_finish() argument
851 if (cs->currbuf) { in fuse_copy_finish()
852 struct pipe_buffer *buf = cs->currbuf; in fuse_copy_finish()
854 if (cs->write) in fuse_copy_finish()
855 buf->len = PAGE_SIZE - cs->len; in fuse_copy_finish()
856 cs->currbuf = NULL; in fuse_copy_finish()
[all …]
/linux/arch/mips/bcm63xx/
H A Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
66 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, in bcm63xx_set_cs_timing() argument
72 if (!is_valid_cs(cs)) in bcm63xx_set_cs_timing()
76 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
83 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
94 int bcm63xx_set_cs_param(unsigned int cs, u32 params) in bcm63xx_set_cs_param() argument
[all …]
/linux/include/linux/mfd/syscon/
H A Datmel-smc.h20 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
21 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
22 ((layout)->timing_regs_offset + ((cs) * 0x14)) argument
23 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
24 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
25 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4) argument
26 #define ATMEL_SMC_CYCLE(cs) (((cs) *
18 ATMEL_SMC_SETUP(cs) global() argument
19 ATMEL_HSMC_SETUP(layout,cs) global() argument
32 ATMEL_SMC_MODE(cs) global() argument
33 ATMEL_HSMC_MODE(layout,cs) global() argument
64 ATMEL_HSMC_TIMINGS(layout,cs) global() argument
[all...]
/linux/net/ceph/
H A Dstring_table.c13 struct ceph_string *cs, *exist; in ceph_find_or_create_string() local
40 cs = kmalloc(sizeof(*cs) + len + 1, GFP_NOFS); in ceph_find_or_create_string()
41 if (!cs) in ceph_find_or_create_string()
44 kref_init(&cs->kref); in ceph_find_or_create_string()
45 cs->len = len; in ceph_find_or_create_string()
46 memcpy(cs->str, str, len); in ceph_find_or_create_string()
47 cs->str[len] = 0; in ceph_find_or_create_string()
68 rb_link_node(&cs->node, parent, p); in ceph_find_or_create_string()
69 rb_insert_color(&cs->node, &string_tree); in ceph_find_or_create_string()
80 kfree(cs); in ceph_find_or_create_string()
[all …]
/linux/fs/xfs/scrub/
H A Dstats.c92 struct xchk_stats *cs, in xchk_stats_format() argument
96 struct xchk_scrub_stats *css = &cs->cs_stats[0]; in xchk_stats_format()
135 struct xchk_stats *cs) in xchk_stats_estimate_bufsize() argument
137 struct xchk_scrub_stats *css = &cs->cs_stats[0]; in xchk_stats_estimate_bufsize()
168 struct xchk_stats *cs) in xchk_stats_clearall() argument
170 struct xchk_scrub_stats *css = &cs->cs_stats[0]; in xchk_stats_clearall()
189 struct xchk_stats *cs, in xchk_stats_merge_one() argument
200 css = &cs->cs_stats[sm->sm_type]; in xchk_stats_merge_one()
248 struct xchk_stats *cs = file->private_data; in xchk_scrub_stats_read() local
261 bufsize = xchk_stats_estimate_bufsize(cs); in xchk_scrub_stats_read()
[all …]
/linux/tools/perf/util/
H A Dcomm.c24 static void comm_strs__remove_if_last(struct comm_str *cs);
44 static refcount_t *comm_str__refcnt(struct comm_str *cs) in comm_str__refcnt() argument
46 return &RC_CHK_ACCESS(cs)->refcnt; in comm_str__refcnt()
49 static const char *comm_str__str(const struct comm_str *cs) in comm_str__str() argument
51 return &RC_CHK_ACCESS(cs)->str[0]; in comm_str__str()
54 static struct comm_str *comm_str__get(struct comm_str *cs) in comm_str__get() argument
58 if (RC_CHK_GET(result, cs)) in comm_str__get()
59 refcount_inc_not_zero(comm_str__refcnt(cs)); in comm_str__get()
64 static void comm_str__put(struct comm_str *cs) in comm_str__put() argument
66 if (!cs) in comm_str__put()
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/linux/Documentation/ABI/testing/
H A Dsysfs-kernel-slab4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
46 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
57 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
69 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
80 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
91 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
103 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
[all …]
/linux/drivers/clocksource/
H A Dtimer-pistachio.c48 struct clocksource cs; member
53 #define to_pistachio_clocksource(cs) \ argument
54 container_of(cs, struct pistachio_clocksource, cs)
68 pistachio_clocksource_read_cycles(struct clocksource *cs) in pistachio_clocksource_read_cycles() argument
70 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles()
90 return pistachio_clocksource_read_cycles(&pcs_gpt.cs); in pistachio_read_sched_clock()
93 static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx, in pistachio_clksrc_set_mode() argument
96 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode()
108 static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx) in pistachio_clksrc_enable() argument
110 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable()
[all …]
/linux/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c163 u32 *cs; in write_timestamp() local
166 cs = intel_ring_begin(rq, 6); in write_timestamp()
167 if (IS_ERR(cs)) in write_timestamp()
168 return PTR_ERR(cs); in write_timestamp()
174 *cs++ = GFX_OP_PIPE_CONTROL(len); in write_timestamp()
175 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | in write_timestamp()
178 *cs++ = slot * sizeof(u32); in write_timestamp()
179 *cs++ = 0; in write_timestamp()
180 *cs++ = 0; in write_timestamp()
181 *cs++ = 0; in write_timestamp()
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