34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value)  in emit_wait()  argument
36 	*cs++ = MI_SEMAPHORE_WAIT |  in emit_wait()
40 	*cs++ = value;  in emit_wait()
41 	*cs++ = offset;  in emit_wait()
42 	*cs++ = 0;  in emit_wait()
44 	return cs;  in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value)  in emit_store()  argument
49 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;  in emit_store()
50 	*cs++ = offset;  in emit_store()
51 	*cs++ = 0;  in emit_store()
52 	*cs++ = value;  in emit_store()
54 	return cs;  in emit_store()
57 static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)  in emit_srm()  argument
59 	*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;  in emit_srm()
60 	*cs++ = i915_mmio_reg_offset(reg);  in emit_srm()
61 	*cs++ = offset;  in emit_srm()
62 	*cs++ = 0;  in emit_srm()
64 	return cs;  in emit_srm()
80 	u32 *cs;  in __measure_timestamps()  local
86 	cs = intel_ring_begin(rq, 28);  in __measure_timestamps()
87 	if (IS_ERR(cs)) {  in __measure_timestamps()
89 		return PTR_ERR(cs);  in __measure_timestamps()
93 	cs = emit_store(cs, offset + 4008, 1);  in __measure_timestamps()
94 	cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);  in __measure_timestamps()
96 	cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);  in __measure_timestamps()
97 	cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);  in __measure_timestamps()
100 	cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);  in __measure_timestamps()
102 	cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);  in __measure_timestamps()
103 	cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);  in __measure_timestamps()
105 	intel_ring_advance(rq, cs);  in __measure_timestamps()
200 	 * the same CS clock.  in live_engine_timestamps()