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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3798cv200.dtsi126 crg: clock-reset-controller@8a22000 { label
127 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
160 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
161 resets = <&crg 0xbc 4>;
168 resets = <&crg 0xbc 8>;
174 resets = <&crg 0xbc 9>;
181 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
182 resets = <&crg 0xbc 6>;
189 resets = <&crg 0xbc 10>;
197 clocks = <&crg HISTB_COMBPHY0_CLK>;
[all …]
H A Dhi3670.dtsi186 compatible = "hisilicon,hi3670-media1-crg", "syscon";
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhi3519.dtsi37 crg: clock-reset-controller@12010000 { label
38 compatible = "hisilicon,hi3519-crg";
55 clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
64 clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
73 clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
82 clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CL
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dhisi-crg.txt1 * HiSilicon Clock and Reset Generator(CRG)
3 The CRG module provides clock and reset signals to various
13 - "hisilicon,hi3516cv300-crg"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
31 A reset signal can be controlled by writing a bit register in the CRG module.
36 Example: CRG nodes
37 CRG: clock-reset-controller@12010000 {
38 compatible = "hisilicon,hi3519-crg";
48 clocks = <&CRG HI3519_I2C0_RST>;
[all …]
H A Dstarfive,jh7110-aoncrg.yaml71 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
76 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
90 #include <dt-bindings/clock/starfive,jh7110-crg.h>
H A Dhi3670-clock.txt16 - "hisilicon,hi3670-media1-crg"
17 - "hisilicon,hi3670-media2-crg"
H A Dstarfive,jh7110-syscrg.yaml82 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
87 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dhisilicon,hi3798cv200-dw-mshc.yaml42 It is integrated into CRG core on the SoC and has to be controlled during tuning.
44 - description: A phandle pointed to the CRG syscon node
45 - description: Sample DLL register offset in CRG address space
80 clocks = <&crg HISTB_MMC_CIU_CLK>,
81 <&crg HISTB_MMC_BIU_CLK>,
82 <&crg HISTB_MMC_SAMPLE_CLK>,
83 <&crg HISTB_MMC_DRV_CLK>;
85 resets = <&crg 0xa0 4>;
H A Dhi3798cv200-dw-mshc.txt28 clocks = <&crg HISTB_MMC_CIU_CLK>,
29 <&crg HISTB_MMC_BIU_CLK>,
30 <&crg HISTB_MMC_SAMPLE_CLK>,
31 <&crg HISTB_MMC_DRV_CLK>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-hisi-inno-usb2.txt39 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
40 resets = <&crg 0xbc 4>;
47 resets = <&crg 0xbc 8>;
53 resets = <&crg 0xbc 9>;
60 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
61 resets = <&crg 0xbc 6>;
68 resets = <&crg 0xbc 10>;
H A Dphy-hi3798cv200-combphy.txt46 clocks = <&crg HISTB_COMBPHY0_CLK>;
47 resets = <&crg 0x188 4>;
55 clocks = <&crg HISTB_COMBPHY1_CLK>;
56 resets = <&crg 0x188 12>;
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dhisilicon-histb-pcie.txt60 clocks = <&crg PCIE_AUX_CLK>,
61 <&crg PCIE_PIPE_CLK>,
62 <&crg PCIE_SYS_CLK>,
63 <&crg PCIE_BUS_CLK>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dhisilicon,histb-xhci.txt36 clocks = <&crg HISTB_USB3_BUS_CLK>,
37 <&crg HISTB_USB3_UTMI_CLK>,
38 <&crg HISTB_USB3_PIPE_CLK>,
39 <&crg HISTB_USB3_SUSPEND_CLK>;
41 resets = <&crg 0xb0 12>;
H A Dhisilicon,hi3798mv200-dwc3.yaml83 resets = <&crg 0xb0 12>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dhisilicon-hix5hd2-gmac.txt51 clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
53 resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
H A Dhisilicon-femac.txt34 clocks = <&crg HI3518EV200_ETH_CLK>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
H A Dhisilicon-femac-mdio.txt15 clocks = <&crg HI3516CV300_MDIO_CLK>;
/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml57 clocks = <&crg 42>;
58 resets = <&crg 0x188 4>;
59 assigned-clocks = <&crg 42>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dhi3516cv300-clock.h9 /* hi3516CV300 core CRG */
33 /* hi3516CV300 sysctrl CRG */
H A Dhistb-clock.h9 /* clocks provided by core CRG */
62 /* clocks provided by mcu CRG */
H A Dhi3670-clock.h21 /* clk in crg clock */
/freebsd/usr.sbin/cron/doc/
H A DMAIL6 From ptsfa!lll-crg!ames!acornrc!bob Wed Dec 31 10:07:08 1986
8 From: lll-crg!ames!acornrc!bob (Bob Weissman)
379 From qantel!lll-crg!ames!uw-beaver!uw-nsr!john Tue Jan 6 23:32:44 1987
381 From: lll-crg!ames!uw-beaver!uw-nsr!john (John Sambrook 5-7433)
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp448 // which needs to happen within the CRG.parseAnalysisRegions() call below. in main()
469 mca::AsmAnalysisRegionGenerator CRG(*TheTarget, SrcMgr, ACtx, *MAI, *STI, in main() local
472 CRG.parseAnalysisRegions(std::move(IPtemp), in main()
540 unsigned AssemblerDialect = CRG.getAssemblerDialect(); in main()
/freebsd/sys/dev/clk/starfive/
H A Djh7110_clk_stg.c27 #include <dt-bindings/clock/starfive,jh7110-crg.h>
H A Djh7110_clk_sys.c31 #include <dt-bindings/clock/starfive,jh7110-crg.h>

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