Lines Matching full:crg
126 crg: clock-reset-controller@8a22000 { label
127 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
160 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
161 resets = <&crg 0xbc 4>;
168 resets = <&crg 0xbc 8>;
174 resets = <&crg 0xbc 9>;
181 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
182 resets = <&crg 0xbc 6>;
189 resets = <&crg 0xbc 10>;
197 clocks = <&crg HISTB_COMBPHY0_CLK>;
198 resets = <&crg 0x188 4>;
199 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
208 clocks = <&crg HISTB_COMBPHY1_CLK>;
209 resets = <&crg 0x188 12>;
210 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
269 clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
281 clocks = <&crg HISTB_I2C0_CLK>;
292 clocks = <&crg HISTB_I2C1_CLK>;
303 clocks = <&crg HISTB_I2C2_CLK>;
314 clocks = <&crg HISTB_I2C3_CLK>;
325 clocks = <&crg HISTB_I2C4_CLK>;
335 clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
346 clocks = <&crg HISTB_SDIO0_BIU_CLK>,
347 <&crg HISTB_SDIO0_CIU_CLK>;
349 resets = <&crg 0x9c 4>;
358 clocks = <&crg HISTB_MMC_CIU_CLK>,
359 <&crg HISTB_MMC_BIU_CLK>,
360 <&crg HISTB_MMC_SAMPLE_CLK>,
361 <&crg HISTB_MMC_DRV_CLK>;
363 resets = <&crg 0xa0 4>;
377 clocks = <&crg HISTB_APB_CLK>;
397 clocks = <&crg HISTB_APB_CLK>;
411 clocks = <&crg HISTB_APB_CLK>;
430 clocks = <&crg HISTB_APB_CLK>;
444 clocks = <&crg HISTB_APB_CLK>;
457 clocks = <&crg HISTB_APB_CLK>;
471 clocks = <&crg HISTB_APB_CLK>;
485 clocks = <&crg HISTB_APB_CLK>;
499 clocks = <&crg HISTB_APB_CLK>;
513 clocks = <&crg HISTB_APB_CLK>;
527 clocks = <&crg HISTB_APB_CLK>;
541 clocks = <&crg HISTB_APB_CLK>;
555 clocks = <&crg HISTB_APB_CLK>;
565 clocks = <&crg HISTB_ETH0_MAC_CLK>,
566 <&crg HISTB_ETH0_MACIF_CLK>;
568 resets = <&crg 0xcc 8>,
569 <&crg 0xcc 10>,
580 clocks = <&crg HISTB_ETH1_MAC_CLK>,
581 <&crg HISTB_ETH1_MACIF_CLK>;
583 resets = <&crg 0xcc 9>,
584 <&crg 0xcc 11>,
616 clocks = <&crg HISTB_PCIE_AUX_CLK>,
617 <&crg HISTB_PCIE_PIPE_CLK>,
618 <&crg HISTB_PCIE_SYS_CLK>,
619 <&crg HISTB_PCIE_BUS_CLK>;
621 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
632 clocks = <&crg HISTB_USB2_BUS_CLK>,
633 <&crg HISTB_USB2_12M_CLK>,
634 <&crg HISTB_USB2_48M_CLK>;
636 resets = <&crg 0xb8 12>;
647 clocks = <&crg HISTB_USB2_BUS_CLK>,
648 <&crg HISTB_USB2_PHY_CLK>,
649 <&crg HISTB_USB2_UTMI_CLK>;
651 resets = <&crg 0xb8 12>,
652 <&crg 0xb8 16>,
653 <&crg 0xb8 13>;