/linux/drivers/net/ethernet/ti/ |
H A D | cpsw_priv.c | 25 #include "cpsw.h" 34 int (*cpsw_slave_index)(struct cpsw_common *cpsw, struct cpsw_priv *priv); 36 void cpsw_intr_enable(struct cpsw_common *cpsw) in cpsw_intr_enable() argument 38 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en); in cpsw_intr_enable() 39 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en); in cpsw_intr_enable() 41 cpdma_ctlr_int_ctrl(cpsw->dma, true); in cpsw_intr_enable() 44 void cpsw_intr_disable(struct cpsw_common *cpsw) in cpsw_intr_disable() argument 46 writel_relaxed(0, &cpsw->wr_regs->tx_en); in cpsw_intr_disable() 47 writel_relaxed(0, &cpsw->wr_regs->rx_en); in cpsw_intr_disable() 49 cpdma_ctlr_int_ctrl(cpsw->dma, false); in cpsw_intr_disable() [all …]
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H A D | cpsw_switchdev.c | 15 #include "cpsw.h" 29 struct cpsw_common *cpsw = priv->cpsw; in cpsw_port_stp_state_set() local 51 ret = cpsw_ale_control_set(cpsw->ale, priv->emac_port, in cpsw_port_stp_state_set() 62 struct cpsw_common *cpsw = priv->cpsw; in cpsw_port_attr_br_flags_set() local 73 cpsw_ale_set_unreg_mcast(cpsw->ale, BIT(priv->emac_port), in cpsw_port_attr_br_flags_set() 121 struct cpsw_common *cpsw = priv->cpsw; in cpsw_get_pvid() local 128 if (cpsw->version == CPSW_VERSION_1) in cpsw_get_pvid() 130 pvid = slave_read(cpsw->slaves + (priv->emac_port - 1), reg); in cpsw_get_pvid() 132 port_vlan_reg = &cpsw->host_port_regs->port_vlan; in cpsw_get_pvid() 143 struct cpsw_common *cpsw = priv->cpsw; in cpsw_set_pvid() local [all …]
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H A D | Makefile | 6 obj-$(CONFIG_TI_CPSW) += cpsw-common.o 7 obj-$(CONFIG_TI_DAVINCI_EMAC) += cpsw-common.o 8 obj-$(CONFIG_TI_CPSW_SWITCHDEV) += cpsw-common.o 14 obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o 17 ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o cpsw_priv.o cpsw_sl.o cpsw_ethtool.o 28 obj-$(CONFIG_TI_K3_AM65_CPSW_NUSS) += ti-am65-cpsw-nuss.o 29 ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o 30 ti-am65-cpsw-nuss-$(CONFIG_TI_AM65_CPSW_QOS) += am65-cpsw-qos.o 31 ti-am65-cpsw-nuss-$(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV) += am65-cpsw-switchdev.o
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H A D | am65-cpsw-switchdev.c | 14 #include "am65-cpsw-nuss.h" 15 #include "am65-cpsw-switchdev.h" 27 struct am65_cpsw_common *cpsw = port->common; in am65_cpsw_port_stp_state_set() local 49 ret = cpsw_ale_control_set(cpsw->ale, port->port_id, in am65_cpsw_port_stp_state_set() 60 struct am65_cpsw_common *cpsw = port->common; in am65_cpsw_port_attr_br_flags_set() local 71 cpsw_ale_set_unreg_mcast(cpsw->ale, BIT(port->port_id), in am65_cpsw_port_attr_br_flags_set() 119 struct am65_cpsw_common *cpsw = port->common; in am65_cpsw_get_pvid() local 120 struct am65_cpsw_host *host_p = am65_common_get_host(cpsw); in am65_cpsw_get_pvid() 135 struct am65_cpsw_common *cpsw = port->common; in am65_cpsw_set_pvid() local 136 struct am65_cpsw_host *host_p = am65_common_get_host(cpsw); in am65_cpsw_set_pvid() [all …]
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H A D | Kconfig | 44 bool "TI CPSW Phy mode Selection (DEPRECATED)" 48 the CPSW. DEPRECATED: use PHY_TI_GMII_SEL. 51 tristate "TI CPSW Switch Support" 60 This driver supports TI's CPSW Ethernet Switch. 63 will be called cpsw. 66 tristate "TI CPSW Switch Support with switchdev" 77 This driver supports TI's CPSW Ethernet Switch. 89 the CPSW Ethernet Switch and Keystone 2 1g/10g Switch Subsystem. 97 tristate "TI K3 AM654x/J721E CPSW Ethernet driver" 114 will be called ti-am65-cpsw-nuss. [all …]
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H A D | cpsw-phy-sel.c | 16 #include "cpsw.h" 165 node = of_parse_phandle(dev->of_node, "cpsw-phy-sel", 0); in cpsw_phy_sel() 167 node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel"); in cpsw_phy_sel() 192 .compatible = "ti,am3352-cpsw-phy-sel", 196 .compatible = "ti,dra7xx-cpsw-phy-sel", 200 .compatible = "ti,am43xx-cpsw-phy-sel", 217 dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n"); in cpsw_phy_sel_probe() 238 .name = "cpsw-phy-sel",
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H A D | am65-cpsw-switchdev.h | 16 int am65_cpsw_switchdev_register_notifiers(struct am65_cpsw_common *cpsw); 17 void am65_cpsw_switchdev_unregister_notifiers(struct am65_cpsw_common *cpsw); 19 static inline int am65_cpsw_switchdev_register_notifiers(struct am65_cpsw_common *cpsw) in am65_cpsw_switchdev_register_notifiers() argument 24 static inline void am65_cpsw_switchdev_unregister_notifiers(struct am65_cpsw_common *cpsw) in am65_cpsw_switchdev_unregister_notifiers() argument
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H A D | am65-cpsw-nuss.c | 40 #include "am65-cpsw-nuss.h" 41 #include "am65-cpsw-switchdev.h" 292 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", in am65_cpsw_nuss_get_ver() 1053 /* VLAN aware CPSW mode is incompatible with some DSA tagging schemes. in am65_cpsw_nuss_ndo_slave_open() 3057 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) in am65_cpsw_register_notifiers() argument 3061 if (AM65_CPSW_IS_CPSW2G(cpsw) || in am65_cpsw_register_notifiers() 3065 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; in am65_cpsw_register_notifiers() 3066 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); in am65_cpsw_register_notifiers() 3068 dev_err(cpsw->dev, "can't register netdevice notifier\n"); in am65_cpsw_register_notifiers() 3072 ret = am65_cpsw_switchdev_register_notifiers(cpsw); in am65_cpsw_register_notifiers() [all …]
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H A D | cpsw_switchdev.h | 12 int cpsw_switchdev_register_notifiers(struct cpsw_common *cpsw); 13 void cpsw_switchdev_unregister_notifiers(struct cpsw_common *cpsw);
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H A D | am65-cpsw-ethtool.c | 13 #include "am65-cpsw-nuss.h" 14 #include "am65-cpsw-qos.h" 36 * @module_id: CPSW module ID 37 * @len: CPSW module registers space length in u32 48 * @hdr: CPSW module header 49 * @start_ofs: CPSW module registers start addr 50 * @end_ofs: CPSW module registers end addr 563 /* update CPSW IP version */ in am65_cpsw_get_regs() 906 /* CPSW Functional Spec states: in am65_cpsw_get_mm_stats()
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H A D | cpsw-common.c | 9 #include "cpsw.h" 93 MODULE_DESCRIPTION("TI CPSW Switch common module");
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H A D | am65-cpsw-nuss.h | 18 #include "am65-cpsw-qos.h" 211 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
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/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,cpsw-switch.yaml | 4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# 7 title: TI SoC Ethernet Switch Controller (CPSW) 24 - const: ti,cpsw-switch 26 - const: ti,am335x-cpsw-switch 27 - const: ti,cpsw-switch 29 - const: ti,am4372-cpsw-switch 30 - const: ti,cpsw-switch 32 - const: ti,dra7-cpsw-switch 33 - const: ti,cpsw-switch 38 The physical base address and size of full the CPSW module IO range [all …]
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H A D | cpsw.txt | 6 "ti,cpsw" for backward compatible 7 "ti,am335x-cpsw" for AM335x controllers 8 "ti,am4372-cpsw" for AM437x controllers 9 "ti,dra7-cpsw" for DRA7x controllers 10 - reg : physical base address and size of the cpsw 22 - cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection 23 device. See also cpsw-phy-sel.txt for its binding. 24 Note that in legacy cases cpsw-phy-sel may be 34 required to be driven so that cpsw data lines 37 driven low so that cpsw slave 0 and phy data [all …]
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H A D | cpsw-phy-sel.txt | 1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED) 5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and 6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform 7 "ti,am43xx-cpsw-phy-sel" for am43xx platform 8 - reg : physical base address and size of the cpsw 18 phy_sel: cpsw-phy-sel@44e10650 { 19 compatible = "ti,am3352-cpsw-phy-sel"; 25 phy_sel: cpsw-phy-sel@44e10650 { 26 compatible = "ti,am3352-cpsw-phy-sel";
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | ti,phy-gmii-sel.yaml | 8 title: CPSW Port's Interface Mode Selection PHY 22 | CPSW | | +---------+ | 41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between 42 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration. 44 CPSW Port's Interface Mode Selection PHY device should defined as child device 45 of SCM node (scm_conf) and can be attached to each CPSW port node using standard 96 description: CPSW port number (starting from 1) 153 - CPSW port number (starting from 1)
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/linux/Documentation/networking/devlink/ |
H A D | am65-nuss-cpsw-switch.rst | 4 am65-cpsw-nuss devlink support 7 This document describes the devlink features implemented by the ``am65-cpsw-nuss`` 13 The ``am65-cpsw-nuss`` driver implements the following driver-specific
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H A D | ti-cpsw-switch.rst | 4 ti-cpsw-switch devlink support 7 This document describes the devlink features implemented by the ``ti-cpsw-switch`` 13 The ``ti-cpsw-switch`` driver implements the following driver-specific
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H A D | index.rst | 94 ti-cpsw-switch 95 am65-nuss-cpsw-switch
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/linux/Documentation/networking/device_drivers/ethernet/ti/ |
H A D | cpsw_switchdev.rst | 4 Texas Instruments CPSW switchdev based ethernet driver 27 working as 2 individual network interfaces. Main differences from legacy CPSW 57 See Documentation/networking/devlink/ti-cpsw-switch.rst 63 which, by default, equal CPSW Port numbers. As result, bridge has to be 92 overwriting of bridge configuration as CPSW switch driver copletly reloads its 95 When the both interfaces joined the bridge - CPSW switch driver will enable
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H A D | am65_nuss_cpsw_switchdev.rst | 4 Texas Instruments K3 AM65 CPSW NUSS switchdev based ethernet driver 29 See Documentation/networking/devlink/am65-nuss-cpsw-switch.rst 42 overwriting of bridge configuration as CPSW switch driver completely reloads its 45 When the both interfaces joined the bridge - CPSW switch driver will enable
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H A D | cpsw.rst | 4 Texas Instruments CPSW ethernet driver 11 The cpsw has 3 CBS shapers for each external ports. This document 12 describes MQPRIO and CBS Qdisc offload configuration for cpsw driver 21 Under consideration two examples with AM572x EVM running cpsw driver 76 - f - fifo (cpsw fifo) 370 | | f3 | | f2 | | f0 |r CPSW r| f3 | | f2 | | f0 | | v
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am335x-sancloud-bbe-common.dtsi | 7 cpsw_default: cpsw-default-pins { 25 cpsw_sleep: cpsw-sleep-pins {
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H A D | am335x-chiliboard.dts | 46 cpsw_default: cpsw-default-pins { 60 cpsw_sleep: cpsw-sleep-pins {
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/linux/drivers/phy/ti/ |
H A D | Kconfig | 112 This driver supports configuring of the TI CPSW Port mode depending on 113 the Ethernet PHY connected to the CPSW Port.
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