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/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi81 clocks = <&cmu CLK_DIV_ACLK_200>;
89 clocks = <&cmu CLK_DIV_ACLK_266>;
117 clocks = <&cmu CLK_DIV_ACLK_160>;
125 clocks = <&cmu CLK_DIV_GDL>;
133 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
161 clocks = <&cmu CLK_SCLK_MFC>;
169 clocks = <&cmu CLK_DIV_ACLK_100>;
191 clocks = <&cmu CLK_DIV_GDR>;
217 clocks = <&cmu CLK_ARM_CLK>;
240 clocks = <&cmu CLK_ARM_CLK>;
[all …]
H A Dexynos3250-artik5-eval.dts49 assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
50 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
51 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
52 <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
53 <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
54 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
/linux/drivers/clk/samsung/
H A Dclk.c69 * @dev: CMU device to enable runtime PM, or NULL if RPM is not needed
70 * @base: Start address (mapped) of CMU registers
242 * Some older DT's have an incorrect CMU resource size which is incompatible
455 * samsung_cmu_register_clocks() - Register all clocks provided in CMU object
457 * @cmu: CMU object with clocks to register
458 * @np: CMU device tree node
461 const struct samsung_cmu_info *cmu, in samsung_cmu_register_clocks() argument
464 if (cmu->auto_clock_gate && samsung_is_auto_capable(np)) in samsung_cmu_register_clocks()
465 ctx->auto_clock_gate = cmu->auto_clock_gate; in samsung_cmu_register_clocks()
467 ctx->gate_dbg_offset = cmu->gate_dbg_offset; in samsung_cmu_register_clocks()
[all …]
H A Dclk-exynos5-subcmu.c17 static const struct exynos5_subcmu_info **cmu; variable
48 * Pass the needed clock provider context and register sub-CMU clocks
62 cmu = _cmu; in exynos5_subcmus_init()
166 if (strcmp(cmu[i]->pd_name, name) == 0) in exynos5_clk_probe()
168 cmu[i], np); in exynos5_clk_probe()
H A Dclk.h334 * struct samsung_cmu_info - all clocks information needed for CMU registration
354 * @clk_name: name of the parent clock needed for CMU register access
358 * @auto_clock_gate: enable auto clock mode for all components in CMU
360 * @option_offset: option reg offset. Enables auto clk mode for entire CMU
440 const struct samsung_cmu_info *cmu,
479 const struct samsung_cmu_info *cmu,
H A Dclk-artpec8.c842 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
1010 .compatible = "axis,artpec8-cmu-cmu",
1013 .compatible = "axis,artpec8-cmu-bus",
1016 .compatible = "axis,artpec8-cmu-core",
1019 .compatible = "axis,artpec8-cmu-cpucl",
1022 .compatible = "axis,artpec8-cmu-fsys",
1025 .compatible = "axis,artpec8-cmu-peri",
1033 .name = "artpec8-cmu",
H A Dclk-exynosautov920.c1012 CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
1141 CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
1243 CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
1345 CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
2006 .compatible = "samsung,exynosautov920-cmu-peric0",
2009 .compatible = "samsung,exynosautov920-cmu-peric1",
2012 .compatible = "samsung,exynosautov920-cmu-misc",
2015 .compatible = "samsung,exynosautov920-cmu-hsi0",
2018 .compatible = "samsung,exynosautov920-cmu-hsi1",
2021 .compatible = "samsung,exynosautov920-cmu-hsi2",
[all …]
H A Dclk-exynos7870.c13 #include <dt-bindings/clock/samsung,exynos7870-cmu.h>
1791 .compatible = "samsung,exynos7870-cmu-mif",
1794 .compatible = "samsung,exynos7870-cmu-dispaud",
1797 .compatible = "samsung,exynos7870-cmu-fsys",
1800 .compatible = "samsung,exynos7870-cmu-g3d",
1803 .compatible = "samsung,exynos7870-cmu-isp",
1806 .compatible = "samsung,exynos7870-cmu-mfcmscl",
1809 .compatible = "samsung,exynos7870-cmu-peri",
1817 .name = "exynos7870-cmu",
H A Dclk-exynosautov9.c966 CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
2162 .compatible = "samsung,exynosautov9-cmu-busmc",
2165 .compatible = "samsung,exynosautov9-cmu-core",
2168 .compatible = "samsung,exynosautov9-cmu-dpum",
2171 .compatible = "samsung,exynosautov9-cmu-fsys0",
2174 .compatible = "samsung,exynosautov9-cmu-fsys1",
2177 .compatible = "samsung,exynosautov9-cmu-fsys2",
2180 .compatible = "samsung,exynosautov9-cmu-peric0",
2183 .compatible = "samsung,exynosautov9-cmu-peric1",
2186 .compatible = "samsung,exynosautov9-cmu-peris",
[all …]
H A Dclk-exynos5-subcmu.h24 const struct exynos5_subcmu_info **cmu);
/linux/Documentation/devicetree/bindings/clock/
H A Daxis,artpec8-clock.yaml13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
14 units, generating clocks for different domains. Those CMU units are modeled
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
31 - axis,artpec8-cmu-cmu
32 - axis,artpec8-cmu-bus
33 - axis,artpec8-cmu-core
34 - axis,artpec8-cmu-cpucl
35 - axis,artpec8-cmu-fsys
36 - axis,artpec8-cmu-imem
37 - axis,artpec8-cmu-peri
[all …]
H A Dsamsung,exynos990-clock.yaml15 Exynos990 clock controller is comprised of several CMU units, generating
16 clocks for different domains. Those CMU units are modeled as separate device
21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
33 - samsung,exynos990-cmu-peric1
34 - samsung,exynos990-cmu-peric0
35 - samsung,exynos990-cmu-hsi0
36 - samsung,exynos990-cmu-peris
37 - samsung,exynos990-cmu-top
66 - samsung,exynos990-cmu-peric1
67 - samsung,exynos990-cmu-peric0
[all …]
H A Dsamsung,exynos8895-clock.yaml15 Exynos8895 clock controller is comprised of several CMU units, generating
16 clocks for different domains. Those CMU units are modeled as separate device
21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
33 - samsung,exynos8895-cmu-fsys0
34 - samsung,exynos8895-cmu-fsys1
35 - samsung,exynos8895-cmu-peric0
36 - samsung,exynos8895-cmu-peric1
37 - samsung,exynos8895-cmu-peris
38 - samsung,exynos8895-cmu-top
66 const: samsung,exynos8895-cmu-fsys0
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H A Dactions,owl-cmu.yaml4 $id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml#
7 title: Actions Semi Owl Clock Management Unit (CMU)
17 include/dt-bindings/clock/actions,s500-cmu.h
18 include/dt-bindings/clock/actions,s700-cmu.h
19 include/dt-bindings/clock/actions,s900-cmu.h
24 - actions,s500-cmu
25 - actions,s700-cmu
26 - actions,s900-cmu
54 compatible = "actions,s900-cmu";
H A Dsamsung,exynos7885-clock.yaml17 Exynos7885 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
34 - samsung,exynos7885-cmu-top
35 - samsung,exynos7885-cmu-core
36 - samsung,exynos7885-cmu-fsys
37 - samsung,exynos7885-cmu-peri
58 const: samsung,exynos7885-cmu-top
74 const: samsung,exynos7885-cmu-core
96 const: samsung,exynos7885-cmu-fsys
[all …]
H A Dsamsung,exynos-clock.yaml23 - samsung,exynos3250-cmu
24 - samsung,exynos3250-cmu-dmc
25 - samsung,exynos3250-cmu-isp
H A Dtesla,fsd-clock.yaml15 (CMU), which generates clocks for various internal SoC blocks.
24 - tesla,fsd-clock-cmu
51 const: tesla,fsd-clock-cmu
/linux/arch/arm64/boot/dts/actions/
H A Ds900.dtsi6 #include <dt-bindings/clock/actions,s900-cmu.h>
125 clocks = <&cmu CLK_UART0>;
133 clocks = <&cmu CLK_UART1>;
141 clocks = <&cmu CLK_UART2>;
149 clocks = <&cmu CLK_UART3>;
157 clocks = <&cmu CLK_UART4>;
165 clocks = <&cmu CLK_UART5>;
173 clocks = <&cmu CLK_UART6>;
184 cmu: clock-controller@e0160000 { label
185 compatible = "actions,s900-cmu";
[all …]
H A Ds700.dtsi6 #include <dt-bindings/clock/actions,s700-cmu.h>
119 clocks = <&cmu CLK_UART0>;
127 clocks = <&cmu CLK_UART1>;
135 clocks = <&cmu CLK_UART2>;
143 clocks = <&cmu CLK_UART3>;
151 clocks = <&cmu CLK_UART4>;
159 clocks = <&cmu CLK_UART5>;
167 clocks = <&cmu CLK_UART6>;
172 cmu: clock-controller@e0168000 { label
173 compatible = "actions,s700-cmu";
[all …]
/linux/arch/arm/boot/dts/actions/
H A Dowl-s500.dtsi8 #include <dt-bindings/clock/actions,s500-cmu.h>
136 clocks = <&cmu CLK_UART0>;
144 clocks = <&cmu CLK_UART1>;
152 clocks = <&cmu CLK_UART2>;
160 clocks = <&cmu CLK_UART3>;
168 clocks = <&cmu CLK_UART4>;
176 clocks = <&cmu CLK_UART5>;
184 clocks = <&cmu CLK_UART6>;
188 cmu: clock-controller@b0160000 { label
189 compatible = "actions,s500-cmu";
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dactions,owl-emac.yaml72 #include <dt-bindings/clock/actions,s500-cmu.h>
80 clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
82 resets = <&cmu RESET_ETHERNET>;
/linux/Documentation/devicetree/bindings/mmc/
H A Dowl-mmc.yaml60 clocks = <&cmu 56>;
61 resets = <&cmu 23>;
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-owl.yaml52 #include <dt-bindings/clock/actions,s900-cmu.h>
58 clocks = <&cmu CLK_I2C0>;
/linux/include/dt-bindings/clock/
H A Dexynos3250.h22 * Main CMU
260 * CMU DMC
281 * CMU ISP
/linux/drivers/phy/
H A Dphy-xgene.c10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
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