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/freebsd/crypto/openssl/doc/designs/quic-design/
H A Dquic-concurrency.md159 As such, the concept of a **Concurrency Management Layer (CML)** is introduced.
160 The CML lives between the APL and the QUIC core code. It is responsible for
168 - **Direct CML (DCML)**, in which core objects are worked on in the same thread
171 - **Worker CML (WCML)**, in which core objects are managed by a worker thread
172 with communication via message passing. This CML is split into a front end
178 CML Design
181 The CML is designed to have as small an API surface area as possible to enable
183 is that complex APL calls are translated into simple operations on the CML.
185 At its core, the CML exposes some number of *pipes*. The number of pipes which
186 can be accessed via the CML varies as connections and streams are created and
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti,lmk04832.yaml119 CML 16 mA 0x07
120 CML 24 mA 0x08
121 CML 32 mA 0x09
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra20-pcie.txt60 - cml (not required for Tegra20)
299 clock-names = "pex", "afi", "pll_e", "cml";
403 clock-names = "pex", "afi", "pll_e", "cml";
499 clock-names = "pex", "afi", "pll_e", "cml";
/freebsd/crypto/openssl/test/recipes/04-test_pem_reading_data/
H A Dcert-threecolumn.pem254 cml
/freebsd/share/man/man4/
H A Duslcom.4191 WIENER Plein & Baus CML Data Logger, RCM Remote,
/freebsd/sys/arm/nvidia/
H A Dtegra_pcie.c903 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); in tegra_pcib_enable_fdt_resources()
1048 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); in tegra_pcib_parse_fdt_resources()
1050 device_printf(sc->dev, "Cannot get 'cml' clock\n"); in tegra_pcib_parse_fdt_resources()
H A Dtegra_ahci.c408 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); in enable_fdt_resources()
/freebsd/usr.sbin/services_mkdb/
H A Dservices723 dna-cml 436/tcp
724 dna-cml 436/udp
1065 tns-cml 590/tcp
1066 tns-cml 590/udp
/freebsd/usr.sbin/bhyve/
H A Dpciids_intel_gpus.h457 /* CML GT1 */
469 /* CML GT2 */
/freebsd/sys/dev/usb/serial/
H A Duslcom.c361 USLCOM_DEV(WIENERPLEINBAUS, CML),
/freebsd/sys/arm64/include/
H A Dcmn600_reg.h160 …MOTE_RNF_SHIFT 28 /* Number of remote RN-F devices in the system when the CML feature is enabled …
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi48 clock-names = "pex", "afi", "pll_e", "cml";
H A Dtegra210.dtsi47 clock-names = "pex", "afi", "pll_e", "cml";
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30.dtsi53 clock-names = "pex", "afi", "pll_e", "cml";
H A Dtegra124.dtsi53 clock-names = "pex", "afi", "pll_e", "cml";
/freebsd/sys/dev/usb/
H A Dusbdevs5022 product WIENERPLEINBAUS CML 0x0015 CML Data Logger
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h37898 … 0x020228UL //Access:RW DataWidth:0x1 // CML Current Control Glo…
37916 … 0x020240UL //Access:RW DataWidth:0x4 // CML Output Channel Power Down 0=CML output ON 1…
38100 …trol of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35]…
38104 …trol of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35]…
38108 …trol of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35]…
38275 …trol of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35]…
38278 …trol of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35]…
38281 …trol of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35]…
38475 … the PLL 0= CMOS Reference clock, output of the differential oscillator 1= CML reference clock, fr…
65936 … (0x1<<7) // Output enables for bidirectional CML refclk buffers.
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/freebsd/share/misc/
H A Dusb_vendors19176 0015 CML Control, Measurement and Data Logging System