1*fb2b8c30SCorvin Köhne /* 2*fb2b8c30SCorvin Köhne * Copyright 2013 Intel Corporation 3*fb2b8c30SCorvin Köhne * All Rights Reserved. 4*fb2b8c30SCorvin Köhne * 5*fb2b8c30SCorvin Köhne * Permission is hereby granted, free of charge, to any person obtaining a 6*fb2b8c30SCorvin Köhne * copy of this software and associated documentation files (the 7*fb2b8c30SCorvin Köhne * "Software"), to deal in the Software without restriction, including 8*fb2b8c30SCorvin Köhne * without limitation the rights to use, copy, modify, merge, publish, 9*fb2b8c30SCorvin Köhne * distribute, sub license, and/or sell copies of the Software, and to 10*fb2b8c30SCorvin Köhne * permit persons to whom the Software is furnished to do so, subject to 11*fb2b8c30SCorvin Köhne * the following conditions: 12*fb2b8c30SCorvin Köhne * 13*fb2b8c30SCorvin Köhne * The above copyright notice and this permission notice (including the 14*fb2b8c30SCorvin Köhne * next paragraph) shall be included in all copies or substantial portions 15*fb2b8c30SCorvin Köhne * of the Software. 16*fb2b8c30SCorvin Köhne * 17*fb2b8c30SCorvin Köhne * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18*fb2b8c30SCorvin Köhne * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19*fb2b8c30SCorvin Köhne * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20*fb2b8c30SCorvin Köhne * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21*fb2b8c30SCorvin Köhne * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22*fb2b8c30SCorvin Köhne * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23*fb2b8c30SCorvin Köhne * DEALINGS IN THE SOFTWARE. 24*fb2b8c30SCorvin Köhne */ 25*fb2b8c30SCorvin Köhne #ifndef __PCIIDS_H__ 26*fb2b8c30SCorvin Köhne #define __PCIIDS_H__ 27*fb2b8c30SCorvin Köhne 28*fb2b8c30SCorvin Köhne #ifdef __KERNEL__ 29*fb2b8c30SCorvin Köhne #define INTEL_VGA_DEVICE(_id, _info) { \ 30*fb2b8c30SCorvin Köhne PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \ 31*fb2b8c30SCorvin Köhne .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \ 32*fb2b8c30SCorvin Köhne .driver_data = (kernel_ulong_t)(_info), \ 33*fb2b8c30SCorvin Köhne } 34*fb2b8c30SCorvin Köhne 35*fb2b8c30SCorvin Köhne #define INTEL_QUANTA_VGA_DEVICE(_info) { \ 36*fb2b8c30SCorvin Köhne .vendor = PCI_VENDOR_ID_INTEL, .device = 0x16a, \ 37*fb2b8c30SCorvin Köhne .subvendor = 0x152d, .subdevice = 0x8990, \ 38*fb2b8c30SCorvin Köhne .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \ 39*fb2b8c30SCorvin Köhne .driver_data = (kernel_ulong_t)(_info), \ 40*fb2b8c30SCorvin Köhne } 41*fb2b8c30SCorvin Köhne #endif 42*fb2b8c30SCorvin Köhne 43*fb2b8c30SCorvin Köhne #define INTEL_I810_IDS(MACRO__, ...) \ 44*fb2b8c30SCorvin Köhne MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \ 45*fb2b8c30SCorvin Köhne MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \ 46*fb2b8c30SCorvin Köhne MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */ 47*fb2b8c30SCorvin Köhne 48*fb2b8c30SCorvin Köhne #define INTEL_I815_IDS(MACRO__, ...) \ 49*fb2b8c30SCorvin Köhne MACRO__(0x1132, ## __VA_ARGS__) /* I815*/ 50*fb2b8c30SCorvin Köhne 51*fb2b8c30SCorvin Köhne #define INTEL_I830_IDS(MACRO__, ...) \ 52*fb2b8c30SCorvin Köhne MACRO__(0x3577, ## __VA_ARGS__) 53*fb2b8c30SCorvin Köhne 54*fb2b8c30SCorvin Köhne #define INTEL_I845G_IDS(MACRO__, ...) \ 55*fb2b8c30SCorvin Köhne MACRO__(0x2562, ## __VA_ARGS__) 56*fb2b8c30SCorvin Köhne 57*fb2b8c30SCorvin Köhne #define INTEL_I85X_IDS(MACRO__, ...) \ 58*fb2b8c30SCorvin Köhne MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \ 59*fb2b8c30SCorvin Köhne MACRO__(0x358e, ## __VA_ARGS__) 60*fb2b8c30SCorvin Köhne 61*fb2b8c30SCorvin Köhne #define INTEL_I865G_IDS(MACRO__, ...) \ 62*fb2b8c30SCorvin Köhne MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */ 63*fb2b8c30SCorvin Köhne 64*fb2b8c30SCorvin Köhne #define INTEL_I915G_IDS(MACRO__, ...) \ 65*fb2b8c30SCorvin Köhne MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \ 66*fb2b8c30SCorvin Köhne MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */ 67*fb2b8c30SCorvin Köhne 68*fb2b8c30SCorvin Köhne #define INTEL_I915GM_IDS(MACRO__, ...) \ 69*fb2b8c30SCorvin Köhne MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */ 70*fb2b8c30SCorvin Köhne 71*fb2b8c30SCorvin Köhne #define INTEL_I945G_IDS(MACRO__, ...) \ 72*fb2b8c30SCorvin Köhne MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */ 73*fb2b8c30SCorvin Köhne 74*fb2b8c30SCorvin Köhne #define INTEL_I945GM_IDS(MACRO__, ...) \ 75*fb2b8c30SCorvin Köhne MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \ 76*fb2b8c30SCorvin Köhne MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */ 77*fb2b8c30SCorvin Köhne 78*fb2b8c30SCorvin Köhne #define INTEL_I965G_IDS(MACRO__, ...) \ 79*fb2b8c30SCorvin Köhne MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \ 80*fb2b8c30SCorvin Köhne MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \ 81*fb2b8c30SCorvin Köhne MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \ 82*fb2b8c30SCorvin Köhne MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */ 83*fb2b8c30SCorvin Köhne 84*fb2b8c30SCorvin Köhne #define INTEL_G33_IDS(MACRO__, ...) \ 85*fb2b8c30SCorvin Köhne MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \ 86*fb2b8c30SCorvin Köhne MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \ 87*fb2b8c30SCorvin Köhne MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */ 88*fb2b8c30SCorvin Köhne 89*fb2b8c30SCorvin Köhne #define INTEL_I965GM_IDS(MACRO__, ...) \ 90*fb2b8c30SCorvin Köhne MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \ 91*fb2b8c30SCorvin Köhne MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */ 92*fb2b8c30SCorvin Köhne 93*fb2b8c30SCorvin Köhne #define INTEL_GM45_IDS(MACRO__, ...) \ 94*fb2b8c30SCorvin Köhne MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */ 95*fb2b8c30SCorvin Köhne 96*fb2b8c30SCorvin Köhne #define INTEL_G45_IDS(MACRO__, ...) \ 97*fb2b8c30SCorvin Köhne MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \ 98*fb2b8c30SCorvin Köhne MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \ 99*fb2b8c30SCorvin Köhne MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \ 100*fb2b8c30SCorvin Köhne MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \ 101*fb2b8c30SCorvin Köhne MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \ 102*fb2b8c30SCorvin Köhne MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */ 103*fb2b8c30SCorvin Köhne 104*fb2b8c30SCorvin Köhne #define INTEL_PNV_G_IDS(MACRO__, ...) \ 105*fb2b8c30SCorvin Köhne MACRO__(0xa001, ## __VA_ARGS__) 106*fb2b8c30SCorvin Köhne 107*fb2b8c30SCorvin Köhne #define INTEL_PNV_M_IDS(MACRO__, ...) \ 108*fb2b8c30SCorvin Köhne MACRO__(0xa011, ## __VA_ARGS__) 109*fb2b8c30SCorvin Köhne 110*fb2b8c30SCorvin Köhne #define INTEL_PNV_IDS(MACRO__, ...) \ 111*fb2b8c30SCorvin Köhne INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \ 112*fb2b8c30SCorvin Köhne INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__) 113*fb2b8c30SCorvin Köhne 114*fb2b8c30SCorvin Köhne #define INTEL_ILK_D_IDS(MACRO__, ...) \ 115*fb2b8c30SCorvin Köhne MACRO__(0x0042, ## __VA_ARGS__) 116*fb2b8c30SCorvin Köhne 117*fb2b8c30SCorvin Köhne #define INTEL_ILK_M_IDS(MACRO__, ...) \ 118*fb2b8c30SCorvin Köhne MACRO__(0x0046, ## __VA_ARGS__) 119*fb2b8c30SCorvin Köhne 120*fb2b8c30SCorvin Köhne #define INTEL_ILK_IDS(MACRO__, ...) \ 121*fb2b8c30SCorvin Köhne INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \ 122*fb2b8c30SCorvin Köhne INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__) 123*fb2b8c30SCorvin Köhne 124*fb2b8c30SCorvin Köhne #define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \ 125*fb2b8c30SCorvin Köhne MACRO__(0x0102, ## __VA_ARGS__), \ 126*fb2b8c30SCorvin Köhne MACRO__(0x010A, ## __VA_ARGS__) 127*fb2b8c30SCorvin Köhne 128*fb2b8c30SCorvin Köhne #define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \ 129*fb2b8c30SCorvin Köhne MACRO__(0x0112, ## __VA_ARGS__), \ 130*fb2b8c30SCorvin Köhne MACRO__(0x0122, ## __VA_ARGS__) 131*fb2b8c30SCorvin Köhne 132*fb2b8c30SCorvin Köhne #define INTEL_SNB_D_IDS(MACRO__, ...) \ 133*fb2b8c30SCorvin Köhne INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 134*fb2b8c30SCorvin Köhne INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) 135*fb2b8c30SCorvin Köhne 136*fb2b8c30SCorvin Köhne #define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \ 137*fb2b8c30SCorvin Köhne MACRO__(0x0106, ## __VA_ARGS__) 138*fb2b8c30SCorvin Köhne 139*fb2b8c30SCorvin Köhne #define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \ 140*fb2b8c30SCorvin Köhne MACRO__(0x0116, ## __VA_ARGS__), \ 141*fb2b8c30SCorvin Köhne MACRO__(0x0126, ## __VA_ARGS__) 142*fb2b8c30SCorvin Köhne 143*fb2b8c30SCorvin Köhne #define INTEL_SNB_M_IDS(MACRO__, ...) \ 144*fb2b8c30SCorvin Köhne INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 145*fb2b8c30SCorvin Köhne INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) 146*fb2b8c30SCorvin Köhne 147*fb2b8c30SCorvin Köhne #define INTEL_SNB_IDS(MACRO__, ...) \ 148*fb2b8c30SCorvin Köhne INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \ 149*fb2b8c30SCorvin Köhne INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__) 150*fb2b8c30SCorvin Köhne 151*fb2b8c30SCorvin Köhne #define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \ 152*fb2b8c30SCorvin Köhne MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */ 153*fb2b8c30SCorvin Köhne 154*fb2b8c30SCorvin Köhne #define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \ 155*fb2b8c30SCorvin Köhne MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */ 156*fb2b8c30SCorvin Köhne 157*fb2b8c30SCorvin Köhne #define INTEL_IVB_M_IDS(MACRO__, ...) \ 158*fb2b8c30SCorvin Köhne INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 159*fb2b8c30SCorvin Köhne INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) 160*fb2b8c30SCorvin Köhne 161*fb2b8c30SCorvin Köhne #define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \ 162*fb2b8c30SCorvin Köhne MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \ 163*fb2b8c30SCorvin Köhne MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */ 164*fb2b8c30SCorvin Köhne 165*fb2b8c30SCorvin Köhne #define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \ 166*fb2b8c30SCorvin Köhne MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \ 167*fb2b8c30SCorvin Köhne MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */ 168*fb2b8c30SCorvin Köhne 169*fb2b8c30SCorvin Köhne #define INTEL_IVB_D_IDS(MACRO__, ...) \ 170*fb2b8c30SCorvin Köhne INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 171*fb2b8c30SCorvin Köhne INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) 172*fb2b8c30SCorvin Köhne 173*fb2b8c30SCorvin Köhne #define INTEL_IVB_IDS(MACRO__, ...) \ 174*fb2b8c30SCorvin Köhne INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \ 175*fb2b8c30SCorvin Köhne INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__) 176*fb2b8c30SCorvin Köhne 177*fb2b8c30SCorvin Köhne #define INTEL_IVB_Q_IDS(MACRO__, ...) \ 178*fb2b8c30SCorvin Köhne INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */ 179*fb2b8c30SCorvin Köhne 180*fb2b8c30SCorvin Köhne #define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \ 181*fb2b8c30SCorvin Köhne MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \ 182*fb2b8c30SCorvin Köhne MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \ 183*fb2b8c30SCorvin Köhne MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \ 184*fb2b8c30SCorvin Köhne MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */ 185*fb2b8c30SCorvin Köhne 186*fb2b8c30SCorvin Köhne #define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \ 187*fb2b8c30SCorvin Köhne MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */ 188*fb2b8c30SCorvin Köhne 189*fb2b8c30SCorvin Köhne #define INTEL_HSW_GT1_IDS(MACRO__, ...) \ 190*fb2b8c30SCorvin Köhne INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 191*fb2b8c30SCorvin Köhne INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 192*fb2b8c30SCorvin Köhne MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \ 193*fb2b8c30SCorvin Köhne MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \ 194*fb2b8c30SCorvin Köhne MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \ 195*fb2b8c30SCorvin Köhne MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \ 196*fb2b8c30SCorvin Köhne MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \ 197*fb2b8c30SCorvin Köhne MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \ 198*fb2b8c30SCorvin Köhne MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \ 199*fb2b8c30SCorvin Köhne MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \ 200*fb2b8c30SCorvin Köhne MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \ 201*fb2b8c30SCorvin Köhne MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \ 202*fb2b8c30SCorvin Köhne MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \ 203*fb2b8c30SCorvin Köhne MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \ 204*fb2b8c30SCorvin Köhne MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \ 205*fb2b8c30SCorvin Köhne MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \ 206*fb2b8c30SCorvin Köhne MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */ 207*fb2b8c30SCorvin Köhne 208*fb2b8c30SCorvin Köhne #define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \ 209*fb2b8c30SCorvin Köhne MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \ 210*fb2b8c30SCorvin Köhne MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \ 211*fb2b8c30SCorvin Köhne MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \ 212*fb2b8c30SCorvin Köhne MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \ 213*fb2b8c30SCorvin Köhne 214*fb2b8c30SCorvin Köhne #define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \ 215*fb2b8c30SCorvin Köhne MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \ 216*fb2b8c30SCorvin Köhne 217*fb2b8c30SCorvin Köhne #define INTEL_HSW_GT2_IDS(MACRO__, ...) \ 218*fb2b8c30SCorvin Köhne INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 219*fb2b8c30SCorvin Köhne INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 220*fb2b8c30SCorvin Köhne MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \ 221*fb2b8c30SCorvin Köhne MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \ 222*fb2b8c30SCorvin Köhne MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \ 223*fb2b8c30SCorvin Köhne MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \ 224*fb2b8c30SCorvin Köhne MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \ 225*fb2b8c30SCorvin Köhne MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \ 226*fb2b8c30SCorvin Köhne MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \ 227*fb2b8c30SCorvin Köhne MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \ 228*fb2b8c30SCorvin Köhne MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \ 229*fb2b8c30SCorvin Köhne MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \ 230*fb2b8c30SCorvin Köhne MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \ 231*fb2b8c30SCorvin Köhne MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \ 232*fb2b8c30SCorvin Köhne MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \ 233*fb2b8c30SCorvin Köhne MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \ 234*fb2b8c30SCorvin Köhne MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */ 235*fb2b8c30SCorvin Köhne 236*fb2b8c30SCorvin Köhne #define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \ 237*fb2b8c30SCorvin Köhne MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \ 238*fb2b8c30SCorvin Köhne MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \ 239*fb2b8c30SCorvin Köhne MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \ 240*fb2b8c30SCorvin Köhne MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \ 241*fb2b8c30SCorvin Köhne MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */ 242*fb2b8c30SCorvin Köhne 243*fb2b8c30SCorvin Köhne #define INTEL_HSW_GT3_IDS(MACRO__, ...) \ 244*fb2b8c30SCorvin Köhne INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 245*fb2b8c30SCorvin Köhne MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \ 246*fb2b8c30SCorvin Köhne MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \ 247*fb2b8c30SCorvin Köhne MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \ 248*fb2b8c30SCorvin Köhne MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \ 249*fb2b8c30SCorvin Köhne MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \ 250*fb2b8c30SCorvin Köhne MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \ 251*fb2b8c30SCorvin Köhne MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \ 252*fb2b8c30SCorvin Köhne MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \ 253*fb2b8c30SCorvin Köhne MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \ 254*fb2b8c30SCorvin Köhne MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \ 255*fb2b8c30SCorvin Köhne MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \ 256*fb2b8c30SCorvin Köhne MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \ 257*fb2b8c30SCorvin Köhne MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \ 258*fb2b8c30SCorvin Köhne MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \ 259*fb2b8c30SCorvin Köhne MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */ 260*fb2b8c30SCorvin Köhne 261*fb2b8c30SCorvin Köhne #define INTEL_HSW_IDS(MACRO__, ...) \ 262*fb2b8c30SCorvin Köhne INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 263*fb2b8c30SCorvin Köhne INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 264*fb2b8c30SCorvin Köhne INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__) 265*fb2b8c30SCorvin Köhne 266*fb2b8c30SCorvin Köhne #define INTEL_VLV_IDS(MACRO__, ...) \ 267*fb2b8c30SCorvin Köhne MACRO__(0x0f30, ## __VA_ARGS__), \ 268*fb2b8c30SCorvin Köhne MACRO__(0x0f31, ## __VA_ARGS__), \ 269*fb2b8c30SCorvin Köhne MACRO__(0x0f32, ## __VA_ARGS__), \ 270*fb2b8c30SCorvin Köhne MACRO__(0x0f33, ## __VA_ARGS__) 271*fb2b8c30SCorvin Köhne 272*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \ 273*fb2b8c30SCorvin Köhne MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \ 274*fb2b8c30SCorvin Köhne MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */ 275*fb2b8c30SCorvin Köhne 276*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \ 277*fb2b8c30SCorvin Köhne MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */ 278*fb2b8c30SCorvin Köhne 279*fb2b8c30SCorvin Köhne #define INTEL_BDW_GT1_IDS(MACRO__, ...) \ 280*fb2b8c30SCorvin Köhne INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 281*fb2b8c30SCorvin Köhne INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 282*fb2b8c30SCorvin Köhne MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \ 283*fb2b8c30SCorvin Köhne MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \ 284*fb2b8c30SCorvin Köhne MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */ 285*fb2b8c30SCorvin Köhne 286*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \ 287*fb2b8c30SCorvin Köhne MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \ 288*fb2b8c30SCorvin Köhne MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */ 289*fb2b8c30SCorvin Köhne 290*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \ 291*fb2b8c30SCorvin Köhne MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */ 292*fb2b8c30SCorvin Köhne 293*fb2b8c30SCorvin Köhne #define INTEL_BDW_GT2_IDS(MACRO__, ...) \ 294*fb2b8c30SCorvin Köhne INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 295*fb2b8c30SCorvin Köhne INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 296*fb2b8c30SCorvin Köhne MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \ 297*fb2b8c30SCorvin Köhne MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \ 298*fb2b8c30SCorvin Köhne MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */ 299*fb2b8c30SCorvin Köhne 300*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \ 301*fb2b8c30SCorvin Köhne MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \ 302*fb2b8c30SCorvin Köhne MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \ 303*fb2b8c30SCorvin Köhne 304*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \ 305*fb2b8c30SCorvin Köhne MACRO__(0x162E, ## __VA_ARGS__) /* ULX */ 306*fb2b8c30SCorvin Köhne 307*fb2b8c30SCorvin Köhne #define INTEL_BDW_GT3_IDS(MACRO__, ...) \ 308*fb2b8c30SCorvin Köhne INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 309*fb2b8c30SCorvin Köhne INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 310*fb2b8c30SCorvin Köhne MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \ 311*fb2b8c30SCorvin Köhne MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \ 312*fb2b8c30SCorvin Köhne MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */ 313*fb2b8c30SCorvin Köhne 314*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \ 315*fb2b8c30SCorvin Köhne MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \ 316*fb2b8c30SCorvin Köhne MACRO__(0x163B, ## __VA_ARGS__) /* Iris */ 317*fb2b8c30SCorvin Köhne 318*fb2b8c30SCorvin Köhne #define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \ 319*fb2b8c30SCorvin Köhne MACRO__(0x163E, ## __VA_ARGS__) /* ULX */ 320*fb2b8c30SCorvin Köhne 321*fb2b8c30SCorvin Köhne #define INTEL_BDW_RSVD_IDS(MACRO__, ...) \ 322*fb2b8c30SCorvin Köhne INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ 323*fb2b8c30SCorvin Köhne INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ 324*fb2b8c30SCorvin Köhne MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \ 325*fb2b8c30SCorvin Köhne MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \ 326*fb2b8c30SCorvin Köhne MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */ 327*fb2b8c30SCorvin Köhne 328*fb2b8c30SCorvin Köhne #define INTEL_BDW_IDS(MACRO__, ...) \ 329*fb2b8c30SCorvin Köhne INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 330*fb2b8c30SCorvin Köhne INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 331*fb2b8c30SCorvin Köhne INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 332*fb2b8c30SCorvin Köhne INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__) 333*fb2b8c30SCorvin Köhne 334*fb2b8c30SCorvin Köhne #define INTEL_CHV_IDS(MACRO__, ...) \ 335*fb2b8c30SCorvin Köhne MACRO__(0x22b0, ## __VA_ARGS__), \ 336*fb2b8c30SCorvin Köhne MACRO__(0x22b1, ## __VA_ARGS__), \ 337*fb2b8c30SCorvin Köhne MACRO__(0x22b2, ## __VA_ARGS__), \ 338*fb2b8c30SCorvin Köhne MACRO__(0x22b3, ## __VA_ARGS__) 339*fb2b8c30SCorvin Köhne 340*fb2b8c30SCorvin Köhne #define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \ 341*fb2b8c30SCorvin Köhne MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \ 342*fb2b8c30SCorvin Köhne MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */ 343*fb2b8c30SCorvin Köhne 344*fb2b8c30SCorvin Köhne #define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \ 345*fb2b8c30SCorvin Köhne MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \ 346*fb2b8c30SCorvin Köhne MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */ 347*fb2b8c30SCorvin Köhne 348*fb2b8c30SCorvin Köhne #define INTEL_SKL_GT1_IDS(MACRO__, ...) \ 349*fb2b8c30SCorvin Köhne INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 350*fb2b8c30SCorvin Köhne INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 351*fb2b8c30SCorvin Köhne MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \ 352*fb2b8c30SCorvin Köhne MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \ 353*fb2b8c30SCorvin Köhne MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \ 354*fb2b8c30SCorvin Köhne MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */ 355*fb2b8c30SCorvin Köhne 356*fb2b8c30SCorvin Köhne #define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \ 357*fb2b8c30SCorvin Köhne MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \ 358*fb2b8c30SCorvin Köhne MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */ 359*fb2b8c30SCorvin Köhne 360*fb2b8c30SCorvin Köhne #define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \ 361*fb2b8c30SCorvin Köhne MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */ 362*fb2b8c30SCorvin Köhne 363*fb2b8c30SCorvin Köhne #define INTEL_SKL_GT2_IDS(MACRO__, ...) \ 364*fb2b8c30SCorvin Köhne INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 365*fb2b8c30SCorvin Köhne INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 366*fb2b8c30SCorvin Köhne MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \ 367*fb2b8c30SCorvin Köhne MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \ 368*fb2b8c30SCorvin Köhne MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \ 369*fb2b8c30SCorvin Köhne MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */ 370*fb2b8c30SCorvin Köhne 371*fb2b8c30SCorvin Köhne #define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \ 372*fb2b8c30SCorvin Köhne MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \ 373*fb2b8c30SCorvin Köhne MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \ 374*fb2b8c30SCorvin Köhne MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */ 375*fb2b8c30SCorvin Köhne 376*fb2b8c30SCorvin Köhne #define INTEL_SKL_GT3_IDS(MACRO__, ...) \ 377*fb2b8c30SCorvin Köhne INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 378*fb2b8c30SCorvin Köhne MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \ 379*fb2b8c30SCorvin Köhne MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \ 380*fb2b8c30SCorvin Köhne MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */ 381*fb2b8c30SCorvin Köhne 382*fb2b8c30SCorvin Köhne #define INTEL_SKL_GT4_IDS(MACRO__, ...) \ 383*fb2b8c30SCorvin Köhne MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \ 384*fb2b8c30SCorvin Köhne MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \ 385*fb2b8c30SCorvin Köhne MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \ 386*fb2b8c30SCorvin Köhne MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */ 387*fb2b8c30SCorvin Köhne 388*fb2b8c30SCorvin Köhne #define INTEL_SKL_IDS(MACRO__, ...) \ 389*fb2b8c30SCorvin Köhne INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 390*fb2b8c30SCorvin Köhne INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 391*fb2b8c30SCorvin Köhne INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 392*fb2b8c30SCorvin Köhne INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__) 393*fb2b8c30SCorvin Köhne 394*fb2b8c30SCorvin Köhne #define INTEL_BXT_IDS(MACRO__, ...) \ 395*fb2b8c30SCorvin Köhne MACRO__(0x0A84, ## __VA_ARGS__), \ 396*fb2b8c30SCorvin Köhne MACRO__(0x1A84, ## __VA_ARGS__), \ 397*fb2b8c30SCorvin Köhne MACRO__(0x1A85, ## __VA_ARGS__), \ 398*fb2b8c30SCorvin Köhne MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \ 399*fb2b8c30SCorvin Köhne MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */ 400*fb2b8c30SCorvin Köhne 401*fb2b8c30SCorvin Köhne #define INTEL_GLK_IDS(MACRO__, ...) \ 402*fb2b8c30SCorvin Köhne MACRO__(0x3184, ## __VA_ARGS__), \ 403*fb2b8c30SCorvin Köhne MACRO__(0x3185, ## __VA_ARGS__) 404*fb2b8c30SCorvin Köhne 405*fb2b8c30SCorvin Köhne #define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \ 406*fb2b8c30SCorvin Köhne MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \ 407*fb2b8c30SCorvin Köhne MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */ 408*fb2b8c30SCorvin Köhne 409*fb2b8c30SCorvin Köhne #define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \ 410*fb2b8c30SCorvin Köhne MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \ 411*fb2b8c30SCorvin Köhne MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */ 412*fb2b8c30SCorvin Köhne 413*fb2b8c30SCorvin Köhne #define INTEL_KBL_GT1_IDS(MACRO__, ...) \ 414*fb2b8c30SCorvin Köhne INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 415*fb2b8c30SCorvin Köhne INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 416*fb2b8c30SCorvin Köhne MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \ 417*fb2b8c30SCorvin Köhne MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \ 418*fb2b8c30SCorvin Köhne MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \ 419*fb2b8c30SCorvin Köhne MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */ 420*fb2b8c30SCorvin Köhne 421*fb2b8c30SCorvin Köhne #define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \ 422*fb2b8c30SCorvin Köhne MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \ 423*fb2b8c30SCorvin Köhne MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */ 424*fb2b8c30SCorvin Köhne 425*fb2b8c30SCorvin Köhne #define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \ 426*fb2b8c30SCorvin Köhne MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */ 427*fb2b8c30SCorvin Köhne 428*fb2b8c30SCorvin Köhne #define INTEL_KBL_GT2_IDS(MACRO__, ...) \ 429*fb2b8c30SCorvin Köhne INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 430*fb2b8c30SCorvin Köhne INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 431*fb2b8c30SCorvin Köhne MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \ 432*fb2b8c30SCorvin Köhne MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \ 433*fb2b8c30SCorvin Köhne MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \ 434*fb2b8c30SCorvin Köhne MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \ 435*fb2b8c30SCorvin Köhne MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */ 436*fb2b8c30SCorvin Köhne 437*fb2b8c30SCorvin Köhne #define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \ 438*fb2b8c30SCorvin Köhne MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */ 439*fb2b8c30SCorvin Köhne 440*fb2b8c30SCorvin Köhne #define INTEL_KBL_GT3_IDS(MACRO__, ...) \ 441*fb2b8c30SCorvin Köhne INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 442*fb2b8c30SCorvin Köhne MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \ 443*fb2b8c30SCorvin Köhne MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */ 444*fb2b8c30SCorvin Köhne 445*fb2b8c30SCorvin Köhne #define INTEL_KBL_GT4_IDS(MACRO__, ...) \ 446*fb2b8c30SCorvin Köhne MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */ 447*fb2b8c30SCorvin Köhne 448*fb2b8c30SCorvin Köhne /* AML/KBL Y GT2 */ 449*fb2b8c30SCorvin Köhne #define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \ 450*fb2b8c30SCorvin Köhne MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \ 451*fb2b8c30SCorvin Köhne MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */ 452*fb2b8c30SCorvin Köhne 453*fb2b8c30SCorvin Köhne /* AML/CFL Y GT2 */ 454*fb2b8c30SCorvin Köhne #define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \ 455*fb2b8c30SCorvin Köhne MACRO__(0x87CA, ## __VA_ARGS__) 456*fb2b8c30SCorvin Köhne 457*fb2b8c30SCorvin Köhne /* CML GT1 */ 458*fb2b8c30SCorvin Köhne #define INTEL_CML_GT1_IDS(MACRO__, ...) \ 459*fb2b8c30SCorvin Köhne MACRO__(0x9BA2, ## __VA_ARGS__), \ 460*fb2b8c30SCorvin Köhne MACRO__(0x9BA4, ## __VA_ARGS__), \ 461*fb2b8c30SCorvin Köhne MACRO__(0x9BA5, ## __VA_ARGS__), \ 462*fb2b8c30SCorvin Köhne MACRO__(0x9BA8, ## __VA_ARGS__) 463*fb2b8c30SCorvin Köhne 464*fb2b8c30SCorvin Köhne #define INTEL_CML_U_GT1_IDS(MACRO__, ...) \ 465*fb2b8c30SCorvin Köhne MACRO__(0x9B21, ## __VA_ARGS__), \ 466*fb2b8c30SCorvin Köhne MACRO__(0x9BAA, ## __VA_ARGS__), \ 467*fb2b8c30SCorvin Köhne MACRO__(0x9BAC, ## __VA_ARGS__) 468*fb2b8c30SCorvin Köhne 469*fb2b8c30SCorvin Köhne /* CML GT2 */ 470*fb2b8c30SCorvin Köhne #define INTEL_CML_GT2_IDS(MACRO__, ...) \ 471*fb2b8c30SCorvin Köhne MACRO__(0x9BC2, ## __VA_ARGS__), \ 472*fb2b8c30SCorvin Köhne MACRO__(0x9BC4, ## __VA_ARGS__), \ 473*fb2b8c30SCorvin Köhne MACRO__(0x9BC5, ## __VA_ARGS__), \ 474*fb2b8c30SCorvin Köhne MACRO__(0x9BC6, ## __VA_ARGS__), \ 475*fb2b8c30SCorvin Köhne MACRO__(0x9BC8, ## __VA_ARGS__), \ 476*fb2b8c30SCorvin Köhne MACRO__(0x9BE6, ## __VA_ARGS__), \ 477*fb2b8c30SCorvin Köhne MACRO__(0x9BF6, ## __VA_ARGS__) 478*fb2b8c30SCorvin Köhne 479*fb2b8c30SCorvin Köhne #define INTEL_CML_U_GT2_IDS(MACRO__, ...) \ 480*fb2b8c30SCorvin Köhne MACRO__(0x9B41, ## __VA_ARGS__), \ 481*fb2b8c30SCorvin Köhne MACRO__(0x9BCA, ## __VA_ARGS__), \ 482*fb2b8c30SCorvin Köhne MACRO__(0x9BCC, ## __VA_ARGS__) 483*fb2b8c30SCorvin Köhne 484*fb2b8c30SCorvin Köhne #define INTEL_CML_IDS(MACRO__, ...) \ 485*fb2b8c30SCorvin Köhne INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 486*fb2b8c30SCorvin Köhne INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 487*fb2b8c30SCorvin Köhne INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 488*fb2b8c30SCorvin Köhne INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__) 489*fb2b8c30SCorvin Köhne 490*fb2b8c30SCorvin Köhne #define INTEL_KBL_IDS(MACRO__, ...) \ 491*fb2b8c30SCorvin Köhne INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 492*fb2b8c30SCorvin Köhne INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 493*fb2b8c30SCorvin Köhne INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 494*fb2b8c30SCorvin Köhne INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \ 495*fb2b8c30SCorvin Köhne INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__) 496*fb2b8c30SCorvin Köhne 497*fb2b8c30SCorvin Köhne /* CFL S */ 498*fb2b8c30SCorvin Köhne #define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \ 499*fb2b8c30SCorvin Köhne MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \ 500*fb2b8c30SCorvin Köhne MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \ 501*fb2b8c30SCorvin Köhne MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */ 502*fb2b8c30SCorvin Köhne 503*fb2b8c30SCorvin Köhne #define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \ 504*fb2b8c30SCorvin Köhne MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \ 505*fb2b8c30SCorvin Köhne MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \ 506*fb2b8c30SCorvin Köhne MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \ 507*fb2b8c30SCorvin Köhne MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \ 508*fb2b8c30SCorvin Köhne MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */ 509*fb2b8c30SCorvin Köhne 510*fb2b8c30SCorvin Köhne /* CFL H */ 511*fb2b8c30SCorvin Köhne #define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \ 512*fb2b8c30SCorvin Köhne MACRO__(0x3E9C, ## __VA_ARGS__) 513*fb2b8c30SCorvin Köhne 514*fb2b8c30SCorvin Köhne #define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \ 515*fb2b8c30SCorvin Köhne MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \ 516*fb2b8c30SCorvin Köhne MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */ 517*fb2b8c30SCorvin Köhne 518*fb2b8c30SCorvin Köhne /* CFL U GT2 */ 519*fb2b8c30SCorvin Köhne #define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \ 520*fb2b8c30SCorvin Köhne MACRO__(0x3EA9, ## __VA_ARGS__) 521*fb2b8c30SCorvin Köhne 522*fb2b8c30SCorvin Köhne /* CFL U GT3 */ 523*fb2b8c30SCorvin Köhne #define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \ 524*fb2b8c30SCorvin Köhne MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \ 525*fb2b8c30SCorvin Köhne MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \ 526*fb2b8c30SCorvin Köhne MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \ 527*fb2b8c30SCorvin Köhne MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */ 528*fb2b8c30SCorvin Köhne 529*fb2b8c30SCorvin Köhne #define INTEL_CFL_IDS(MACRO__, ...) \ 530*fb2b8c30SCorvin Köhne INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 531*fb2b8c30SCorvin Köhne INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 532*fb2b8c30SCorvin Köhne INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 533*fb2b8c30SCorvin Köhne INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 534*fb2b8c30SCorvin Köhne INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 535*fb2b8c30SCorvin Köhne INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \ 536*fb2b8c30SCorvin Köhne INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__) 537*fb2b8c30SCorvin Köhne 538*fb2b8c30SCorvin Köhne /* WHL/CFL U GT1 */ 539*fb2b8c30SCorvin Köhne #define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \ 540*fb2b8c30SCorvin Köhne MACRO__(0x3EA1, ## __VA_ARGS__), \ 541*fb2b8c30SCorvin Köhne MACRO__(0x3EA4, ## __VA_ARGS__) 542*fb2b8c30SCorvin Köhne 543*fb2b8c30SCorvin Köhne /* WHL/CFL U GT2 */ 544*fb2b8c30SCorvin Köhne #define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \ 545*fb2b8c30SCorvin Köhne MACRO__(0x3EA0, ## __VA_ARGS__), \ 546*fb2b8c30SCorvin Köhne MACRO__(0x3EA3, ## __VA_ARGS__) 547*fb2b8c30SCorvin Köhne 548*fb2b8c30SCorvin Köhne /* WHL/CFL U GT3 */ 549*fb2b8c30SCorvin Köhne #define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \ 550*fb2b8c30SCorvin Köhne MACRO__(0x3EA2, ## __VA_ARGS__) 551*fb2b8c30SCorvin Köhne 552*fb2b8c30SCorvin Köhne #define INTEL_WHL_IDS(MACRO__, ...) \ 553*fb2b8c30SCorvin Köhne INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 554*fb2b8c30SCorvin Köhne INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ 555*fb2b8c30SCorvin Köhne INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__) 556*fb2b8c30SCorvin Köhne 557*fb2b8c30SCorvin Köhne /* CNL */ 558*fb2b8c30SCorvin Köhne #define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \ 559*fb2b8c30SCorvin Köhne MACRO__(0x5A44, ## __VA_ARGS__), \ 560*fb2b8c30SCorvin Köhne MACRO__(0x5A4C, ## __VA_ARGS__), \ 561*fb2b8c30SCorvin Köhne MACRO__(0x5A54, ## __VA_ARGS__), \ 562*fb2b8c30SCorvin Köhne MACRO__(0x5A5C, ## __VA_ARGS__) 563*fb2b8c30SCorvin Köhne 564*fb2b8c30SCorvin Köhne #define INTEL_CNL_IDS(MACRO__, ...) \ 565*fb2b8c30SCorvin Köhne INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ 566*fb2b8c30SCorvin Köhne MACRO__(0x5A40, ## __VA_ARGS__), \ 567*fb2b8c30SCorvin Köhne MACRO__(0x5A41, ## __VA_ARGS__), \ 568*fb2b8c30SCorvin Köhne MACRO__(0x5A42, ## __VA_ARGS__), \ 569*fb2b8c30SCorvin Köhne MACRO__(0x5A49, ## __VA_ARGS__), \ 570*fb2b8c30SCorvin Köhne MACRO__(0x5A4A, ## __VA_ARGS__), \ 571*fb2b8c30SCorvin Köhne MACRO__(0x5A50, ## __VA_ARGS__), \ 572*fb2b8c30SCorvin Köhne MACRO__(0x5A51, ## __VA_ARGS__), \ 573*fb2b8c30SCorvin Köhne MACRO__(0x5A52, ## __VA_ARGS__), \ 574*fb2b8c30SCorvin Köhne MACRO__(0x5A59, ## __VA_ARGS__), \ 575*fb2b8c30SCorvin Köhne MACRO__(0x5A5A, ## __VA_ARGS__) 576*fb2b8c30SCorvin Köhne 577*fb2b8c30SCorvin Köhne /* ICL */ 578*fb2b8c30SCorvin Köhne #define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \ 579*fb2b8c30SCorvin Köhne MACRO__(0x8A50, ## __VA_ARGS__), \ 580*fb2b8c30SCorvin Köhne MACRO__(0x8A52, ## __VA_ARGS__), \ 581*fb2b8c30SCorvin Köhne MACRO__(0x8A53, ## __VA_ARGS__), \ 582*fb2b8c30SCorvin Köhne MACRO__(0x8A54, ## __VA_ARGS__), \ 583*fb2b8c30SCorvin Köhne MACRO__(0x8A56, ## __VA_ARGS__), \ 584*fb2b8c30SCorvin Köhne MACRO__(0x8A57, ## __VA_ARGS__), \ 585*fb2b8c30SCorvin Köhne MACRO__(0x8A58, ## __VA_ARGS__), \ 586*fb2b8c30SCorvin Köhne MACRO__(0x8A59, ## __VA_ARGS__), \ 587*fb2b8c30SCorvin Köhne MACRO__(0x8A5A, ## __VA_ARGS__), \ 588*fb2b8c30SCorvin Köhne MACRO__(0x8A5B, ## __VA_ARGS__), \ 589*fb2b8c30SCorvin Köhne MACRO__(0x8A5C, ## __VA_ARGS__), \ 590*fb2b8c30SCorvin Köhne MACRO__(0x8A70, ## __VA_ARGS__), \ 591*fb2b8c30SCorvin Köhne MACRO__(0x8A71, ## __VA_ARGS__) 592*fb2b8c30SCorvin Köhne 593*fb2b8c30SCorvin Köhne #define INTEL_ICL_IDS(MACRO__, ...) \ 594*fb2b8c30SCorvin Köhne INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ 595*fb2b8c30SCorvin Köhne MACRO__(0x8A51, ## __VA_ARGS__), \ 596*fb2b8c30SCorvin Köhne MACRO__(0x8A5D, ## __VA_ARGS__) 597*fb2b8c30SCorvin Köhne 598*fb2b8c30SCorvin Köhne /* EHL */ 599*fb2b8c30SCorvin Köhne #define INTEL_EHL_IDS(MACRO__, ...) \ 600*fb2b8c30SCorvin Köhne MACRO__(0x4541, ## __VA_ARGS__), \ 601*fb2b8c30SCorvin Köhne MACRO__(0x4551, ## __VA_ARGS__), \ 602*fb2b8c30SCorvin Köhne MACRO__(0x4555, ## __VA_ARGS__), \ 603*fb2b8c30SCorvin Köhne MACRO__(0x4557, ## __VA_ARGS__), \ 604*fb2b8c30SCorvin Köhne MACRO__(0x4570, ## __VA_ARGS__), \ 605*fb2b8c30SCorvin Köhne MACRO__(0x4571, ## __VA_ARGS__) 606*fb2b8c30SCorvin Köhne 607*fb2b8c30SCorvin Köhne /* JSL */ 608*fb2b8c30SCorvin Köhne #define INTEL_JSL_IDS(MACRO__, ...) \ 609*fb2b8c30SCorvin Köhne MACRO__(0x4E51, ## __VA_ARGS__), \ 610*fb2b8c30SCorvin Köhne MACRO__(0x4E55, ## __VA_ARGS__), \ 611*fb2b8c30SCorvin Köhne MACRO__(0x4E57, ## __VA_ARGS__), \ 612*fb2b8c30SCorvin Köhne MACRO__(0x4E61, ## __VA_ARGS__), \ 613*fb2b8c30SCorvin Köhne MACRO__(0x4E71, ## __VA_ARGS__) 614*fb2b8c30SCorvin Köhne 615*fb2b8c30SCorvin Köhne /* TGL */ 616*fb2b8c30SCorvin Köhne #define INTEL_TGL_GT1_IDS(MACRO__, ...) \ 617*fb2b8c30SCorvin Köhne MACRO__(0x9A60, ## __VA_ARGS__), \ 618*fb2b8c30SCorvin Köhne MACRO__(0x9A68, ## __VA_ARGS__), \ 619*fb2b8c30SCorvin Köhne MACRO__(0x9A70, ## __VA_ARGS__) 620*fb2b8c30SCorvin Köhne 621*fb2b8c30SCorvin Köhne #define INTEL_TGL_GT2_IDS(MACRO__, ...) \ 622*fb2b8c30SCorvin Köhne MACRO__(0x9A40, ## __VA_ARGS__), \ 623*fb2b8c30SCorvin Köhne MACRO__(0x9A49, ## __VA_ARGS__), \ 624*fb2b8c30SCorvin Köhne MACRO__(0x9A59, ## __VA_ARGS__), \ 625*fb2b8c30SCorvin Köhne MACRO__(0x9A78, ## __VA_ARGS__), \ 626*fb2b8c30SCorvin Köhne MACRO__(0x9AC0, ## __VA_ARGS__), \ 627*fb2b8c30SCorvin Köhne MACRO__(0x9AC9, ## __VA_ARGS__), \ 628*fb2b8c30SCorvin Köhne MACRO__(0x9AD9, ## __VA_ARGS__), \ 629*fb2b8c30SCorvin Köhne MACRO__(0x9AF8, ## __VA_ARGS__) 630*fb2b8c30SCorvin Köhne 631*fb2b8c30SCorvin Köhne #define INTEL_TGL_IDS(MACRO__, ...) \ 632*fb2b8c30SCorvin Köhne INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ 633*fb2b8c30SCorvin Köhne INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) 634*fb2b8c30SCorvin Köhne 635*fb2b8c30SCorvin Köhne /* RKL */ 636*fb2b8c30SCorvin Köhne #define INTEL_RKL_IDS(MACRO__, ...) \ 637*fb2b8c30SCorvin Köhne MACRO__(0x4C80, ## __VA_ARGS__), \ 638*fb2b8c30SCorvin Köhne MACRO__(0x4C8A, ## __VA_ARGS__), \ 639*fb2b8c30SCorvin Köhne MACRO__(0x4C8B, ## __VA_ARGS__), \ 640*fb2b8c30SCorvin Köhne MACRO__(0x4C8C, ## __VA_ARGS__), \ 641*fb2b8c30SCorvin Köhne MACRO__(0x4C90, ## __VA_ARGS__), \ 642*fb2b8c30SCorvin Köhne MACRO__(0x4C9A, ## __VA_ARGS__) 643*fb2b8c30SCorvin Köhne 644*fb2b8c30SCorvin Köhne /* DG1 */ 645*fb2b8c30SCorvin Köhne #define INTEL_DG1_IDS(MACRO__, ...) \ 646*fb2b8c30SCorvin Köhne MACRO__(0x4905, ## __VA_ARGS__), \ 647*fb2b8c30SCorvin Köhne MACRO__(0x4906, ## __VA_ARGS__), \ 648*fb2b8c30SCorvin Köhne MACRO__(0x4907, ## __VA_ARGS__), \ 649*fb2b8c30SCorvin Köhne MACRO__(0x4908, ## __VA_ARGS__), \ 650*fb2b8c30SCorvin Köhne MACRO__(0x4909, ## __VA_ARGS__) 651*fb2b8c30SCorvin Köhne 652*fb2b8c30SCorvin Köhne /* ADL-S */ 653*fb2b8c30SCorvin Köhne #define INTEL_ADLS_IDS(MACRO__, ...) \ 654*fb2b8c30SCorvin Köhne MACRO__(0x4680, ## __VA_ARGS__), \ 655*fb2b8c30SCorvin Köhne MACRO__(0x4682, ## __VA_ARGS__), \ 656*fb2b8c30SCorvin Köhne MACRO__(0x4688, ## __VA_ARGS__), \ 657*fb2b8c30SCorvin Köhne MACRO__(0x468A, ## __VA_ARGS__), \ 658*fb2b8c30SCorvin Köhne MACRO__(0x468B, ## __VA_ARGS__), \ 659*fb2b8c30SCorvin Köhne MACRO__(0x4690, ## __VA_ARGS__), \ 660*fb2b8c30SCorvin Köhne MACRO__(0x4692, ## __VA_ARGS__), \ 661*fb2b8c30SCorvin Köhne MACRO__(0x4693, ## __VA_ARGS__) 662*fb2b8c30SCorvin Köhne 663*fb2b8c30SCorvin Köhne /* ADL-P */ 664*fb2b8c30SCorvin Köhne #define INTEL_ADLP_IDS(MACRO__, ...) \ 665*fb2b8c30SCorvin Köhne MACRO__(0x46A0, ## __VA_ARGS__), \ 666*fb2b8c30SCorvin Köhne MACRO__(0x46A1, ## __VA_ARGS__), \ 667*fb2b8c30SCorvin Köhne MACRO__(0x46A2, ## __VA_ARGS__), \ 668*fb2b8c30SCorvin Köhne MACRO__(0x46A3, ## __VA_ARGS__), \ 669*fb2b8c30SCorvin Köhne MACRO__(0x46A6, ## __VA_ARGS__), \ 670*fb2b8c30SCorvin Köhne MACRO__(0x46A8, ## __VA_ARGS__), \ 671*fb2b8c30SCorvin Köhne MACRO__(0x46AA, ## __VA_ARGS__), \ 672*fb2b8c30SCorvin Köhne MACRO__(0x462A, ## __VA_ARGS__), \ 673*fb2b8c30SCorvin Köhne MACRO__(0x4626, ## __VA_ARGS__), \ 674*fb2b8c30SCorvin Köhne MACRO__(0x4628, ## __VA_ARGS__), \ 675*fb2b8c30SCorvin Köhne MACRO__(0x46B0, ## __VA_ARGS__), \ 676*fb2b8c30SCorvin Köhne MACRO__(0x46B1, ## __VA_ARGS__), \ 677*fb2b8c30SCorvin Köhne MACRO__(0x46B2, ## __VA_ARGS__), \ 678*fb2b8c30SCorvin Köhne MACRO__(0x46B3, ## __VA_ARGS__), \ 679*fb2b8c30SCorvin Köhne MACRO__(0x46C0, ## __VA_ARGS__), \ 680*fb2b8c30SCorvin Köhne MACRO__(0x46C1, ## __VA_ARGS__), \ 681*fb2b8c30SCorvin Köhne MACRO__(0x46C2, ## __VA_ARGS__), \ 682*fb2b8c30SCorvin Köhne MACRO__(0x46C3, ## __VA_ARGS__) 683*fb2b8c30SCorvin Köhne 684*fb2b8c30SCorvin Köhne /* ADL-N */ 685*fb2b8c30SCorvin Köhne #define INTEL_ADLN_IDS(MACRO__, ...) \ 686*fb2b8c30SCorvin Köhne MACRO__(0x46D0, ## __VA_ARGS__), \ 687*fb2b8c30SCorvin Köhne MACRO__(0x46D1, ## __VA_ARGS__), \ 688*fb2b8c30SCorvin Köhne MACRO__(0x46D2, ## __VA_ARGS__), \ 689*fb2b8c30SCorvin Köhne MACRO__(0x46D3, ## __VA_ARGS__), \ 690*fb2b8c30SCorvin Köhne MACRO__(0x46D4, ## __VA_ARGS__) 691*fb2b8c30SCorvin Köhne 692*fb2b8c30SCorvin Köhne /* RPL-S */ 693*fb2b8c30SCorvin Köhne #define INTEL_RPLS_IDS(MACRO__, ...) \ 694*fb2b8c30SCorvin Köhne MACRO__(0xA780, ## __VA_ARGS__), \ 695*fb2b8c30SCorvin Köhne MACRO__(0xA781, ## __VA_ARGS__), \ 696*fb2b8c30SCorvin Köhne MACRO__(0xA782, ## __VA_ARGS__), \ 697*fb2b8c30SCorvin Köhne MACRO__(0xA783, ## __VA_ARGS__), \ 698*fb2b8c30SCorvin Köhne MACRO__(0xA788, ## __VA_ARGS__), \ 699*fb2b8c30SCorvin Köhne MACRO__(0xA789, ## __VA_ARGS__), \ 700*fb2b8c30SCorvin Köhne MACRO__(0xA78A, ## __VA_ARGS__), \ 701*fb2b8c30SCorvin Köhne MACRO__(0xA78B, ## __VA_ARGS__) 702*fb2b8c30SCorvin Köhne 703*fb2b8c30SCorvin Köhne /* RPL-U */ 704*fb2b8c30SCorvin Köhne #define INTEL_RPLU_IDS(MACRO__, ...) \ 705*fb2b8c30SCorvin Köhne MACRO__(0xA721, ## __VA_ARGS__), \ 706*fb2b8c30SCorvin Köhne MACRO__(0xA7A1, ## __VA_ARGS__), \ 707*fb2b8c30SCorvin Köhne MACRO__(0xA7A9, ## __VA_ARGS__), \ 708*fb2b8c30SCorvin Köhne MACRO__(0xA7AC, ## __VA_ARGS__), \ 709*fb2b8c30SCorvin Köhne MACRO__(0xA7AD, ## __VA_ARGS__) 710*fb2b8c30SCorvin Köhne 711*fb2b8c30SCorvin Köhne /* RPL-P */ 712*fb2b8c30SCorvin Köhne #define INTEL_RPLP_IDS(MACRO__, ...) \ 713*fb2b8c30SCorvin Köhne MACRO__(0xA720, ## __VA_ARGS__), \ 714*fb2b8c30SCorvin Köhne MACRO__(0xA7A0, ## __VA_ARGS__), \ 715*fb2b8c30SCorvin Köhne MACRO__(0xA7A8, ## __VA_ARGS__), \ 716*fb2b8c30SCorvin Köhne MACRO__(0xA7AA, ## __VA_ARGS__), \ 717*fb2b8c30SCorvin Köhne MACRO__(0xA7AB, ## __VA_ARGS__) 718*fb2b8c30SCorvin Köhne 719*fb2b8c30SCorvin Köhne /* DG2 */ 720*fb2b8c30SCorvin Köhne #define INTEL_DG2_G10_D_IDS(MACRO__, ...) \ 721*fb2b8c30SCorvin Köhne MACRO__(0x56A0, ## __VA_ARGS__), \ 722*fb2b8c30SCorvin Köhne MACRO__(0x56A1, ## __VA_ARGS__), \ 723*fb2b8c30SCorvin Köhne MACRO__(0x56A2, ## __VA_ARGS__) 724*fb2b8c30SCorvin Köhne 725*fb2b8c30SCorvin Köhne #define INTEL_DG2_G10_E_IDS(MACRO__, ...) \ 726*fb2b8c30SCorvin Köhne MACRO__(0x56BE, ## __VA_ARGS__), \ 727*fb2b8c30SCorvin Köhne MACRO__(0x56BF, ## __VA_ARGS__) 728*fb2b8c30SCorvin Köhne 729*fb2b8c30SCorvin Köhne #define INTEL_DG2_G10_M_IDS(MACRO__, ...) \ 730*fb2b8c30SCorvin Köhne MACRO__(0x5690, ## __VA_ARGS__), \ 731*fb2b8c30SCorvin Köhne MACRO__(0x5691, ## __VA_ARGS__), \ 732*fb2b8c30SCorvin Köhne MACRO__(0x5692, ## __VA_ARGS__) 733*fb2b8c30SCorvin Köhne 734*fb2b8c30SCorvin Köhne #define INTEL_DG2_G10_IDS(MACRO__, ...) \ 735*fb2b8c30SCorvin Köhne INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \ 736*fb2b8c30SCorvin Köhne INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \ 737*fb2b8c30SCorvin Köhne INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__) 738*fb2b8c30SCorvin Köhne 739*fb2b8c30SCorvin Köhne #define INTEL_DG2_G11_D_IDS(MACRO__, ...) \ 740*fb2b8c30SCorvin Köhne MACRO__(0x56A5, ## __VA_ARGS__), \ 741*fb2b8c30SCorvin Köhne MACRO__(0x56A6, ## __VA_ARGS__), \ 742*fb2b8c30SCorvin Köhne MACRO__(0x56B0, ## __VA_ARGS__), \ 743*fb2b8c30SCorvin Köhne MACRO__(0x56B1, ## __VA_ARGS__) 744*fb2b8c30SCorvin Köhne 745*fb2b8c30SCorvin Köhne #define INTEL_DG2_G11_E_IDS(MACRO__, ...) \ 746*fb2b8c30SCorvin Köhne MACRO__(0x56BA, ## __VA_ARGS__), \ 747*fb2b8c30SCorvin Köhne MACRO__(0x56BB, ## __VA_ARGS__), \ 748*fb2b8c30SCorvin Köhne MACRO__(0x56BC, ## __VA_ARGS__), \ 749*fb2b8c30SCorvin Köhne MACRO__(0x56BD, ## __VA_ARGS__) 750*fb2b8c30SCorvin Köhne 751*fb2b8c30SCorvin Köhne #define INTEL_DG2_G11_M_IDS(MACRO__, ...) \ 752*fb2b8c30SCorvin Köhne MACRO__(0x5693, ## __VA_ARGS__), \ 753*fb2b8c30SCorvin Köhne MACRO__(0x5694, ## __VA_ARGS__), \ 754*fb2b8c30SCorvin Köhne MACRO__(0x5695, ## __VA_ARGS__) 755*fb2b8c30SCorvin Köhne 756*fb2b8c30SCorvin Köhne #define INTEL_DG2_G11_IDS(MACRO__, ...) \ 757*fb2b8c30SCorvin Köhne INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \ 758*fb2b8c30SCorvin Köhne INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \ 759*fb2b8c30SCorvin Köhne INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__) 760*fb2b8c30SCorvin Köhne 761*fb2b8c30SCorvin Köhne #define INTEL_DG2_G12_D_IDS(MACRO__, ...) \ 762*fb2b8c30SCorvin Köhne MACRO__(0x56A3, ## __VA_ARGS__), \ 763*fb2b8c30SCorvin Köhne MACRO__(0x56A4, ## __VA_ARGS__), \ 764*fb2b8c30SCorvin Köhne MACRO__(0x56B2, ## __VA_ARGS__), \ 765*fb2b8c30SCorvin Köhne MACRO__(0x56B3, ## __VA_ARGS__) 766*fb2b8c30SCorvin Köhne 767*fb2b8c30SCorvin Köhne #define INTEL_DG2_G12_M_IDS(MACRO__, ...) \ 768*fb2b8c30SCorvin Köhne MACRO__(0x5696, ## __VA_ARGS__), \ 769*fb2b8c30SCorvin Köhne MACRO__(0x5697, ## __VA_ARGS__) 770*fb2b8c30SCorvin Köhne 771*fb2b8c30SCorvin Köhne #define INTEL_DG2_G12_IDS(MACRO__, ...) \ 772*fb2b8c30SCorvin Köhne INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \ 773*fb2b8c30SCorvin Köhne INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__) 774*fb2b8c30SCorvin Köhne 775*fb2b8c30SCorvin Köhne #define INTEL_DG2_D_IDS(MACRO__, ...) \ 776*fb2b8c30SCorvin Köhne INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \ 777*fb2b8c30SCorvin Köhne INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \ 778*fb2b8c30SCorvin Köhne INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__) 779*fb2b8c30SCorvin Köhne 780*fb2b8c30SCorvin Köhne #define INTEL_DG2_IDS(MACRO__, ...) \ 781*fb2b8c30SCorvin Köhne INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ 782*fb2b8c30SCorvin Köhne INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ 783*fb2b8c30SCorvin Köhne INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) 784*fb2b8c30SCorvin Köhne 785*fb2b8c30SCorvin Köhne #define INTEL_ATS_M150_IDS(MACRO__, ...) \ 786*fb2b8c30SCorvin Köhne MACRO__(0x56C0, ## __VA_ARGS__), \ 787*fb2b8c30SCorvin Köhne MACRO__(0x56C2, ## __VA_ARGS__) 788*fb2b8c30SCorvin Köhne 789*fb2b8c30SCorvin Köhne #define INTEL_ATS_M75_IDS(MACRO__, ...) \ 790*fb2b8c30SCorvin Köhne MACRO__(0x56C1, ## __VA_ARGS__) 791*fb2b8c30SCorvin Köhne 792*fb2b8c30SCorvin Köhne #define INTEL_ATS_M_IDS(MACRO__, ...) \ 793*fb2b8c30SCorvin Köhne INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \ 794*fb2b8c30SCorvin Köhne INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) 795*fb2b8c30SCorvin Köhne 796*fb2b8c30SCorvin Köhne /* ARL */ 797*fb2b8c30SCorvin Köhne #define INTEL_ARL_H_IDS(MACRO__, ...) \ 798*fb2b8c30SCorvin Köhne MACRO__(0x7D51, ## __VA_ARGS__), \ 799*fb2b8c30SCorvin Köhne MACRO__(0x7DD1, ## __VA_ARGS__) 800*fb2b8c30SCorvin Köhne 801*fb2b8c30SCorvin Köhne #define INTEL_ARL_U_IDS(MACRO__, ...) \ 802*fb2b8c30SCorvin Köhne MACRO__(0x7D41, ## __VA_ARGS__) \ 803*fb2b8c30SCorvin Köhne 804*fb2b8c30SCorvin Köhne #define INTEL_ARL_S_IDS(MACRO__, ...) \ 805*fb2b8c30SCorvin Köhne MACRO__(0x7D67, ## __VA_ARGS__), \ 806*fb2b8c30SCorvin Köhne MACRO__(0xB640, ## __VA_ARGS__) 807*fb2b8c30SCorvin Köhne 808*fb2b8c30SCorvin Köhne #define INTEL_ARL_IDS(MACRO__, ...) \ 809*fb2b8c30SCorvin Köhne INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \ 810*fb2b8c30SCorvin Köhne INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \ 811*fb2b8c30SCorvin Köhne INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__) 812*fb2b8c30SCorvin Köhne 813*fb2b8c30SCorvin Köhne /* MTL */ 814*fb2b8c30SCorvin Köhne #define INTEL_MTL_U_IDS(MACRO__, ...) \ 815*fb2b8c30SCorvin Köhne MACRO__(0x7D40, ## __VA_ARGS__), \ 816*fb2b8c30SCorvin Köhne MACRO__(0x7D45, ## __VA_ARGS__) 817*fb2b8c30SCorvin Köhne 818*fb2b8c30SCorvin Köhne #define INTEL_MTL_IDS(MACRO__, ...) \ 819*fb2b8c30SCorvin Köhne INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \ 820*fb2b8c30SCorvin Köhne MACRO__(0x7D55, ## __VA_ARGS__), \ 821*fb2b8c30SCorvin Köhne MACRO__(0x7D60, ## __VA_ARGS__), \ 822*fb2b8c30SCorvin Köhne MACRO__(0x7DD5, ## __VA_ARGS__) 823*fb2b8c30SCorvin Köhne 824*fb2b8c30SCorvin Köhne /* PVC */ 825*fb2b8c30SCorvin Köhne #define INTEL_PVC_IDS(MACRO__, ...) \ 826*fb2b8c30SCorvin Köhne MACRO__(0x0B69, ## __VA_ARGS__), \ 827*fb2b8c30SCorvin Köhne MACRO__(0x0B6E, ## __VA_ARGS__), \ 828*fb2b8c30SCorvin Köhne MACRO__(0x0BD4, ## __VA_ARGS__), \ 829*fb2b8c30SCorvin Köhne MACRO__(0x0BD5, ## __VA_ARGS__), \ 830*fb2b8c30SCorvin Köhne MACRO__(0x0BD6, ## __VA_ARGS__), \ 831*fb2b8c30SCorvin Köhne MACRO__(0x0BD7, ## __VA_ARGS__), \ 832*fb2b8c30SCorvin Köhne MACRO__(0x0BD8, ## __VA_ARGS__), \ 833*fb2b8c30SCorvin Köhne MACRO__(0x0BD9, ## __VA_ARGS__), \ 834*fb2b8c30SCorvin Köhne MACRO__(0x0BDA, ## __VA_ARGS__), \ 835*fb2b8c30SCorvin Köhne MACRO__(0x0BDB, ## __VA_ARGS__), \ 836*fb2b8c30SCorvin Köhne MACRO__(0x0BE0, ## __VA_ARGS__), \ 837*fb2b8c30SCorvin Köhne MACRO__(0x0BE1, ## __VA_ARGS__), \ 838*fb2b8c30SCorvin Köhne MACRO__(0x0BE5, ## __VA_ARGS__) 839*fb2b8c30SCorvin Köhne 840*fb2b8c30SCorvin Köhne /* LNL */ 841*fb2b8c30SCorvin Köhne #define INTEL_LNL_IDS(MACRO__, ...) \ 842*fb2b8c30SCorvin Köhne MACRO__(0x6420, ## __VA_ARGS__), \ 843*fb2b8c30SCorvin Köhne MACRO__(0x64A0, ## __VA_ARGS__), \ 844*fb2b8c30SCorvin Köhne MACRO__(0x64B0, ## __VA_ARGS__) 845*fb2b8c30SCorvin Köhne 846*fb2b8c30SCorvin Köhne /* BMG */ 847*fb2b8c30SCorvin Köhne #define INTEL_BMG_IDS(MACRO__, ...) \ 848*fb2b8c30SCorvin Köhne MACRO__(0xE202, ## __VA_ARGS__), \ 849*fb2b8c30SCorvin Köhne MACRO__(0xE20B, ## __VA_ARGS__), \ 850*fb2b8c30SCorvin Köhne MACRO__(0xE20C, ## __VA_ARGS__), \ 851*fb2b8c30SCorvin Köhne MACRO__(0xE20D, ## __VA_ARGS__), \ 852*fb2b8c30SCorvin Köhne MACRO__(0xE210, ## __VA_ARGS__), \ 853*fb2b8c30SCorvin Köhne MACRO__(0xE211, ## __VA_ARGS__), \ 854*fb2b8c30SCorvin Köhne MACRO__(0xE212, ## __VA_ARGS__), \ 855*fb2b8c30SCorvin Köhne MACRO__(0xE215, ## __VA_ARGS__), \ 856*fb2b8c30SCorvin Köhne MACRO__(0xE216, ## __VA_ARGS__) 857*fb2b8c30SCorvin Köhne 858*fb2b8c30SCorvin Köhne /* PTL */ 859*fb2b8c30SCorvin Köhne #define INTEL_PTL_IDS(MACRO__, ...) \ 860*fb2b8c30SCorvin Köhne MACRO__(0xB080, ## __VA_ARGS__), \ 861*fb2b8c30SCorvin Köhne MACRO__(0xB081, ## __VA_ARGS__), \ 862*fb2b8c30SCorvin Köhne MACRO__(0xB082, ## __VA_ARGS__), \ 863*fb2b8c30SCorvin Köhne MACRO__(0xB083, ## __VA_ARGS__), \ 864*fb2b8c30SCorvin Köhne MACRO__(0xB084, ## __VA_ARGS__), \ 865*fb2b8c30SCorvin Köhne MACRO__(0xB085, ## __VA_ARGS__), \ 866*fb2b8c30SCorvin Köhne MACRO__(0xB086, ## __VA_ARGS__), \ 867*fb2b8c30SCorvin Köhne MACRO__(0xB087, ## __VA_ARGS__), \ 868*fb2b8c30SCorvin Köhne MACRO__(0xB08F, ## __VA_ARGS__), \ 869*fb2b8c30SCorvin Köhne MACRO__(0xB090, ## __VA_ARGS__), \ 870*fb2b8c30SCorvin Köhne MACRO__(0xB0A0, ## __VA_ARGS__), \ 871*fb2b8c30SCorvin Köhne MACRO__(0xB0B0, ## __VA_ARGS__) 872*fb2b8c30SCorvin Köhne 873*fb2b8c30SCorvin Köhne #endif /* __PCIIDS_H__ */ 874