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Searched full:clk_top_syspll3_d2 (Results 1 – 16 of 16) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-mt65xx.txt31 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
62 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
H A Dmediatek,spi-mt65xx.yaml108 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dmt7629-clk.h43 #define CLK_TOP_SYSPLL3_D2 33 macro
H A Dmt6797-clk.h57 #define CLK_TOP_SYSPLL3_D2 47 macro
H A Dmt7622-clk.h37 #define CLK_TOP_SYSPLL3_D2 25 macro
H A Dmediatek,mt6795-clk.h60 #define CLK_TOP_SYSPLL3_D2 49 macro
H A Dmt8173-clk.h62 #define CLK_TOP_SYSPLL3_D2 52 macro
H A Dmt6765-clk.h46 #define CLK_TOP_SYSPLL3_D2 11 macro
H A Dmediatek,mt8365-clk.h26 #define CLK_TOP_SYSPLL3_D2 16 macro
H A Dmt2712-clk.h45 #define CLK_TOP_SYSPLL3_D2 14 macro
H A Dmt2701-clk.h23 #define CLK_TOP_SYSPLL3_D2 13 macro
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt2701.dtsi342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
415 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
H A Dmt7623.dtsi487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
566 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
580 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
H A Dmt7629.dtsi281 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7622.dtsi498 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
590 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
H A Dmt8173.dtsi770 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,