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Searched full:clk_peri_pwm5 (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-pericfg.h12 #define CLK_PERI_PWM5 6 macro
H A Dmt8135-clk.h164 #define CLK_PERI_PWM5 26 macro
H A Dmediatek,mt6795-clk.h181 #define CLK_PERI_PWM5 6 macro
H A Dmt8173-clk.h200 #define CLK_PERI_PWM5 7 macro
H A Dmt2712-clk.h246 #define CLK_PERI_PWM5 7 macro
H A Dmt2701-clk.h228 #define CLK_PERI_PWM5 7 macro
/linux/Documentation/devicetree/bindings/pwm/
H A Dmediatek,mt2712-pwm.yaml93 <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,
/linux/drivers/clk/mediatek/
H A Dclk-mt8173-pericfg.c57 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
H A Dclk-mt6795-pericfg.c46 GATE_PERI(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
H A Dclk-mt6735-pericfg.c36 GATE_MTK(CLK_PERI_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
H A Dclk-mt8135.c475 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
H A Dclk-mt2701.c849 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
H A Dclk-mt2712.c892 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi489 <&pericfg CLK_PERI_PWM5>,