Home
last modified time | relevance | path

Searched full:clk_peri_pwm4 (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-pericfg.h11 #define CLK_PERI_PWM4 5 macro
H A Dmt8135-clk.h165 #define CLK_PERI_PWM4 27 macro
H A Dmediatek,mt6795-clk.h180 #define CLK_PERI_PWM4 5 macro
H A Dmt8173-clk.h199 #define CLK_PERI_PWM4 6 macro
H A Dmt2712-clk.h245 #define CLK_PERI_PWM4 6 macro
H A Dmt2701-clk.h227 #define CLK_PERI_PWM4 6 macro
/linux/Documentation/devicetree/bindings/pwm/
H A Dmediatek,mt2712-pwm.yaml93 <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,
/linux/drivers/clk/mediatek/
H A Dclk-mt8173-pericfg.c56 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
H A Dclk-mt6795-pericfg.c45 GATE_PERI(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
H A Dclk-mt6735-pericfg.c35 GATE_MTK(CLK_PERI_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
H A Dclk-mt8135.c476 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
H A Dclk-mt2701.c850 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
H A Dclk-mt2712.c891 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi488 <&pericfg CLK_PERI_PWM4>,