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Searched full:clk_mm_disp_wdma0 (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,wdma.yaml85 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c37 GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
H A Dclk-mt8186-mm.c38 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "top_disp", 5),
H A Dclk-mt8183-mm.c61 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
H A Dclk-mt8192-mm.c48 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
H A Dclk-mt6795-mm.c54 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
H A Dclk-mt6797-mm.c54 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
H A Dclk-mt6779-mm.c61 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
H A Dclk-mt8173-mm.c57 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
H A Dclk-mt2712-mm.c65 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h236 #define CLK_MM_DISP_WDMA0 22 macro
H A Dmediatek,mt6795-clk.h240 #define CLK_MM_DISP_WDMA0 21 macro
H A Dmt8173-clk.h268 #define CLK_MM_DISP_WDMA0 21 macro
H A Dmt6765-clk.h262 #define CLK_MM_DISP_WDMA0 11 macro
H A Dmt8183-clk.h333 #define CLK_MM_DISP_WDMA0 24 macro
H A Dmt2712-clk.h322 #define CLK_MM_DISP_WDMA0 21 macro
H A Dmt6779-clk.h365 #define CLK_MM_DISP_WDMA0 25 macro
H A Dmt8186-clk.h306 #define CLK_MM_DISP_WDMA0 5 macro
H A Dmt8192-clk.h429 #define CLK_MM_DISP_WDMA0 5 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi787 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
H A Dmt8173.dtsi1129 clocks = <&mmsys CLK_MM_DISP_WDMA0>;