1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7870 SoC device tree source 4 * 5 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 6 * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org> 7 */ 8 9#include <dt-bindings/clock/samsung,exynos7870-cmu.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7870"; 14 #address-cells = <2>; 15 #size-cells = <1>; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 pinctrl0 = &pinctrl_alive; 21 pinctrl1 = &pinctrl_dispaud; 22 pinctrl2 = &pinctrl_ese; 23 pinctrl3 = &pinctrl_fsys; 24 pinctrl4 = &pinctrl_mif; 25 pinctrl5 = &pinctrl_nfc; 26 pinctrl6 = &pinctrl_top; 27 pinctrl7 = &pinctrl_touch; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu-map { 35 cluster0 { 36 core0 { 37 cpu = <&cpu0>; 38 }; 39 core1 { 40 cpu = <&cpu1>; 41 }; 42 core2 { 43 cpu = <&cpu2>; 44 }; 45 core3 { 46 cpu = <&cpu3>; 47 }; 48 }; 49 50 cluster1 { 51 core0 { 52 cpu = <&cpu4>; 53 }; 54 core1 { 55 cpu = <&cpu5>; 56 }; 57 core2 { 58 cpu = <&cpu6>; 59 }; 60 core3 { 61 cpu = <&cpu7>; 62 }; 63 }; 64 }; 65 66 cpu0: cpu@0 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0>; 70 enable-method = "psci"; 71 }; 72 73 cpu1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x1>; 77 enable-method = "psci"; 78 }; 79 80 cpu2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x2>; 84 enable-method = "psci"; 85 }; 86 87 cpu3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x3>; 91 enable-method = "psci"; 92 }; 93 94 cpu4: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 }; 100 101 cpu5: cpu@101 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x101>; 105 enable-method = "psci"; 106 }; 107 108 cpu6: cpu@102 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x102>; 112 enable-method = "psci"; 113 }; 114 115 cpu7: cpu@103 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x103>; 119 enable-method = "psci"; 120 }; 121 }; 122 123 oscclk: oscclk { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 }; 127 128 psci { 129 compatible = "arm,psci"; 130 method = "smc"; 131 cpu_suspend = <0xc4000001>; 132 cpu_off = <0x84000002>; 133 cpu_on = <0xc4000003>; 134 }; 135 136 soc: soc@0 { 137 compatible = "simple-bus"; 138 ranges = <0x0 0x0 0x0 0x20000000>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 142 chipid@10100000 { 143 compatible = "samsung,exynos7870-chipid", 144 "samsung,exynos4210-chipid"; 145 reg = <0x10100000 0x100>; 146 }; 147 148 cmu_peri: clock-controller@101f0000 { 149 compatible = "samsung,exynos7870-cmu-peri"; 150 reg = <0x101f0000 0x1000>; 151 #clock-cells = <1>; 152 153 clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", 154 "spi3", "spi4", "uart0", "uart1", "uart2"; 155 clocks = <&oscclk>, 156 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, 157 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, 158 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, 159 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, 160 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, 161 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, 162 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, 163 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, 164 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; 165 }; 166 167 cmu_mif: clock-controller@10460000 { 168 compatible = "samsung,exynos7870-cmu-mif"; 169 reg = <0x10460000 0x1000>; 170 #clock-cells = <1>; 171 172 clock-names = "oscclk"; 173 clocks = <&oscclk>; 174 }; 175 176 pmu_system_controller: system-controller@10480000 { 177 compatible = "samsung,exynos7870-pmu", 178 "samsung,exynos7-pmu", "syscon"; 179 reg = <0x10480000 0x10000>; 180 181 mipi_phy: mipi-phy { 182 compatible = "samsung,exynos7870-mipi-video-phy"; 183 #phy-cells = <1>; 184 185 samsung,cam0-sysreg = <&syscon_cam0>; 186 samsung,disp-sysreg = <&syscon_disp>; 187 }; 188 189 reboot-mode { 190 compatible = "syscon-reboot-mode"; 191 offset = <0x080c>; 192 mode-bootloader = <0x1234567d>; 193 mode-download = <0x12345671>; 194 mode-recovery = <0x12345674>; 195 }; 196 }; 197 198 gic: interrupt-controller@104e1000 { 199 compatible = "arm,cortex-a15-gic"; 200 reg = <0x104e1000 0x1000>, 201 <0x104e2000 0x1000>, 202 <0x104e4000 0x2000>, 203 <0x104e6000 0x2000>; 204 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 205 IRQ_TYPE_LEVEL_HIGH)>; 206 interrupt-controller; 207 #address-cells = <0>; 208 #interrupt-cells = <3>; 209 }; 210 211 hsi2c0: i2c@10510000 { 212 compatible = "samsung,exynos7870-hsi2c", 213 "samsung,exynos7-hsi2c"; 214 reg = <0x10510000 0x2000>; 215 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 216 217 pinctrl-names = "default"; 218 pinctrl-0 = <&hsi2c0_bus>; 219 220 clock-names = "hsi2c"; 221 clocks = <&cmu_mif CLK_GOUT_MIF_HSI2C_IPCLK>; 222 223 status = "disabled"; 224 }; 225 226 pinctrl_mif: pinctrl@10530000 { 227 compatible = "samsung,exynos7870-pinctrl"; 228 reg = <0x10530000 0x1000>; 229 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 230 }; 231 232 gpu: gpu@11400000 { 233 compatible = "samsung,exynos7870-mali", "arm,mali-t830"; 234 reg = <0x11400000 0x5000>; 235 interrupt-names = "job", "mmu", "gpu"; 236 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 239 240 clock-names = "core", "bus"; 241 clocks = <&cmu_g3d CLK_GOUT_G3D_CLK>, 242 <&cmu_g3d CLK_GOUT_G3D_ASYNCS_D0_CLK>; 243 244 status = "disabled"; 245 }; 246 247 cmu_g3d: clock-controller@11460000 { 248 compatible = "samsung,exynos7870-cmu-g3d"; 249 reg = <0x11460000 0x1000>; 250 #clock-cells = <1>; 251 252 clock-names = "oscclk", "switch"; 253 clocks = <&oscclk>, 254 <&cmu_mif CLK_GOUT_MIF_CMU_G3D_SWITCH>; 255 }; 256 257 cmu_mfcmscl: clock-controller@12cb0000 { 258 compatible = "samsung,exynos7870-cmu-mfcmscl"; 259 reg = <0x12cb0000 0x1000>; 260 #clock-cells = <1>; 261 262 clock-names = "oscclk", "mfc", "mscl"; 263 clocks = <&oscclk>, 264 <&cmu_mif CLK_GOUT_MIF_CMU_MFCMSCL_MFC>, 265 <&cmu_mif CLK_GOUT_MIF_CMU_MFCMSCL_MSCL>; 266 }; 267 268 mmc0: mmc@13540000 { 269 compatible = "samsung,exynos7870-dw-mshc-smu"; 270 reg = <0x13540000 0x2000>; 271 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 272 273 clock-names = "biu", "ciu"; 274 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC0_ACLK>, 275 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC0>; 276 277 status = "disabled"; 278 }; 279 280 mmc1: mmc@13550000 { 281 compatible = "samsung,exynos7870-dw-mshc-smu"; 282 reg = <0x13550000 0x2000>; 283 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 284 285 clock-names = "biu", "ciu"; 286 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC1_ACLK>, 287 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC1>; 288 289 status = "disabled"; 290 }; 291 292 mmc2: mmc@13560000 { 293 compatible = "samsung,exynos7870-dw-mshc-smu"; 294 reg = <0x13560000 0x2000>; 295 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 296 297 clock-names = "biu", "ciu"; 298 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC2_ACLK>, 299 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_MMC2>; 300 301 status = "disabled"; 302 }; 303 304 usbdrd_phy: phy@135c0000 { 305 compatible = "samsung,exynos7870-usbdrd-phy"; 306 reg = <0x135c0000 0x100>; 307 #phy-cells = <1>; 308 309 clock-names = "phy", "ref"; 310 clocks = <&cmu_fsys CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER>, 311 <&cmu_fsys CLK_GOUT_FSYS_MUX_USB_PLL>; 312 313 samsung,pmu-syscon = <&pmu_system_controller>; 314 }; 315 316 usbdrd: usb@13600000 { 317 compatible = "samsung,exynos7870-dwusb3"; 318 ranges = <0x0 0x13600000 0x10000>; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 322 clock-names = "bus_early", "ref", "ctrl"; 323 clocks = <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD>, 324 <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK>, 325 <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL>; 326 327 status = "disabled"; 328 329 usb@0 { 330 compatible = "snps,dwc3"; 331 reg = <0x0 0x10000>; 332 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 333 334 phy-names = "usb2-phy"; 335 phys = <&usbdrd_phy 0>; 336 337 usb-role-switch; 338 snps,usb2-gadget-lpm-disable; 339 }; 340 }; 341 342 cmu_fsys: clock-controller@13730000 { 343 compatible = "samsung,exynos7870-cmu-fsys"; 344 reg = <0x13730000 0x1000>; 345 #clock-cells = <1>; 346 347 clock-names = "oscclk", "bus", "usb20drd"; 348 clocks = <&oscclk>, 349 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_BUS>, 350 <&cmu_mif CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK>; 351 }; 352 353 pinctrl_fsys: pinctrl@13750000 { 354 compatible = "samsung,exynos7870-pinctrl"; 355 reg = <0x13750000 0x1000>; 356 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 357 }; 358 359 serial0: serial@13800000 { 360 compatible = "samsung,exynos7870-uart", 361 "samsung,exynos8895-uart"; 362 reg = <0x13800000 0x100>; 363 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 364 365 pinctrl-names = "default"; 366 pinctrl-0 = <&uart0_bus>; 367 368 clock-names = "uart", "clk_uart_baud0"; 369 clocks = <&cmu_peri CLK_GOUT_PERI_UART0_PCLK>, 370 <&cmu_peri CLK_GOUT_PERI_UART0_EXT_UCLK>; 371 372 samsung,uart-fifosize = <16>; 373 374 status = "disabled"; 375 }; 376 377 serial1: serial@13810000 { 378 compatible = "samsung,exynos7870-uart", 379 "samsung,exynos8895-uart"; 380 reg = <0x13810000 0x100>; 381 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 382 383 pinctrl-names = "default"; 384 pinctrl-0 = <&uart1_bus>; 385 386 clock-names = "uart", "clk_uart_baud0"; 387 clocks = <&cmu_peri CLK_GOUT_PERI_UART1_PCLK>, 388 <&cmu_peri CLK_GOUT_PERI_UART1_EXT_UCLK>; 389 390 samsung,uart-fifosize = <256>; 391 392 status = "disabled"; 393 }; 394 395 serial2: serial@13820000 { 396 compatible = "samsung,exynos7870-uart", 397 "samsung,exynos8895-uart"; 398 reg = <0x13820000 0x100>; 399 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 400 401 pinctrl-names = "default"; 402 pinctrl-0 = <&uart2_bus>; 403 404 clock-names = "uart", "clk_uart_baud0"; 405 clocks = <&cmu_peri CLK_GOUT_PERI_UART2_PCLK>, 406 <&cmu_peri CLK_GOUT_PERI_UART2_EXT_UCLK>; 407 408 samsung,uart-fifosize = <256>; 409 410 status = "disabled"; 411 }; 412 413 i2c0: i2c@13830000 { 414 compatible = "samsung,exynos7870-i2c", 415 "samsung,s3c2440-i2c"; 416 reg = <0x13830000 0x100>; 417 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 418 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c0_bus>; 421 422 clock-names = "i2c"; 423 clocks = <&cmu_peri CLK_GOUT_PERI_I2C0_PCLK>; 424 425 status = "disabled"; 426 }; 427 428 i2c1: i2c@13840000 { 429 compatible = "samsung,exynos7870-i2c", 430 "samsung,s3c2440-i2c"; 431 reg = <0x13840000 0x100>; 432 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 433 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2c1_bus>; 436 437 clock-names = "i2c"; 438 clocks = <&cmu_peri CLK_GOUT_PERI_I2C1_PCLK>; 439 440 status = "disabled"; 441 }; 442 443 i2c2: i2c@13850000 { 444 compatible = "samsung,exynos7870-i2c", 445 "samsung,s3c2440-i2c"; 446 reg = <0x13850000 0x100>; 447 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; 448 449 pinctrl-names = "default"; 450 pinctrl-0 = <&i2c2_bus>; 451 452 clock-names = "i2c"; 453 clocks = <&cmu_peri CLK_GOUT_PERI_I2C2_PCLK>; 454 455 status = "disabled"; 456 }; 457 458 i2c3: i2c@13860000 { 459 compatible = "samsung,exynos7870-i2c", 460 "samsung,s3c2440-i2c"; 461 reg = <0x13860000 0x100>; 462 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; 463 464 pinctrl-names = "default"; 465 pinctrl-0 = <&i2c3_bus>; 466 467 clock-names = "i2c"; 468 clocks = <&cmu_peri CLK_GOUT_PERI_I2C3_PCLK>; 469 470 status = "disabled"; 471 }; 472 473 i2c4: i2c@13870000 { 474 compatible = "samsung,exynos7870-i2c", 475 "samsung,s3c2440-i2c"; 476 reg = <0x13870000 0x100>; 477 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; 478 479 pinctrl-names = "default"; 480 pinctrl-0 = <&i2c4_bus>; 481 482 clock-names = "i2c"; 483 clocks = <&cmu_peri CLK_GOUT_PERI_I2C4_PCLK>; 484 485 status = "disabled"; 486 }; 487 488 i2c5: i2c@13880000 { 489 compatible = "samsung,exynos7870-i2c", 490 "samsung,s3c2440-i2c"; 491 reg = <0x13880000 0x100>; 492 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 493 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c5_bus>; 496 497 clock-names = "i2c"; 498 clocks = <&cmu_peri CLK_GOUT_PERI_I2C5_PCLK>; 499 500 status = "disabled"; 501 }; 502 503 i2c6: i2c@13890000 { 504 compatible = "samsung,exynos7870-i2c", 505 "samsung,s3c2440-i2c"; 506 reg = <0x13890000 0x100>; 507 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 508 509 pinctrl-names = "default"; 510 pinctrl-0 = <&i2c6_bus>; 511 512 clock-names = "i2c"; 513 clocks = <&cmu_peri CLK_GOUT_PERI_I2C6_PCLK>; 514 515 status = "disabled"; 516 }; 517 518 hsi2c1: i2c@138a0000 { 519 compatible = "samsung,exynos7870-hsi2c", 520 "samsung,exynos7-hsi2c"; 521 reg = <0x138a0000 0x1000>; 522 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 523 524 pinctrl-names = "default"; 525 pinctrl-0 = <&hsi2c1_bus>; 526 527 clock-names = "hsi2c"; 528 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C1_IPCLK>; 529 530 status = "disabled"; 531 }; 532 533 hsi2c2: i2c@138b0000 { 534 compatible = "samsung,exynos7870-hsi2c", 535 "samsung,exynos7-hsi2c"; 536 reg = <0x138b0000 0x1000>; 537 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>; 538 539 pinctrl-names = "default"; 540 pinctrl-0 = <&hsi2c2_bus>; 541 542 clock-names = "hsi2c"; 543 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C2_IPCLK>; 544 545 status = "disabled"; 546 }; 547 548 hsi2c3: i2c@138c0000 { 549 compatible = "samsung,exynos7870-hsi2c", 550 "samsung,exynos7-hsi2c"; 551 reg = <0x138c0000 0x1000>; 552 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 553 554 pinctrl-names = "default"; 555 pinctrl-0 = <&hsi2c3_bus>; 556 557 clock-names = "hsi2c"; 558 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C3_IPCLK>; 559 560 status = "disabled"; 561 }; 562 563 i2c7: i2c@138d0000 { 564 compatible = "samsung,exynos7870-i2c", 565 "samsung,s3c2440-i2c"; 566 reg = <0x138d0000 0x100>; 567 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 568 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c7_bus>; 571 572 clock-names = "i2c"; 573 clocks = <&cmu_peri CLK_GOUT_PERI_I2C7_PCLK>; 574 575 status = "disabled"; 576 }; 577 578 i2c8: i2c@138e0000 { 579 compatible = "samsung,exynos7870-i2c", 580 "samsung,s3c2440-i2c"; 581 reg = <0x138e0000 0x100>; 582 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 583 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c8_bus>; 586 587 clock-names = "i2c"; 588 clocks = <&cmu_peri CLK_GOUT_PERI_I2C8_PCLK>; 589 590 status = "disabled"; 591 }; 592 593 hsi2c4: i2c@138f0000 { 594 compatible = "samsung,exynos7870-hsi2c", 595 "samsung,exynos7-hsi2c"; 596 reg = <0x138f0000 0x1000>; 597 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 598 599 pinctrl-names = "default"; 600 pinctrl-0 = <&hsi2c4_bus>; 601 602 clock-names = "hsi2c"; 603 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C4_IPCLK>; 604 605 status = "disabled"; 606 }; 607 608 hsi2c5: i2c@13950000 { 609 compatible = "samsung,exynos7870-hsi2c", 610 "samsung,exynos7-hsi2c"; 611 reg = <0x13950000 0x1000>; 612 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 613 614 pinctrl-names = "default"; 615 pinctrl-0 = <&hsi2c5_bus>; 616 617 clock-names = "hsi2c"; 618 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C5_IPCLK>; 619 620 status = "disabled"; 621 }; 622 623 hsi2c6: i2c@13960000 { 624 compatible = "samsung,exynos7870-hsi2c", 625 "samsung,exynos7-hsi2c"; 626 reg = <0x13960000 0x1000>; 627 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 628 629 pinctrl-names = "default"; 630 pinctrl-0 = <&hsi2c6_bus>; 631 632 clock-names = "hsi2c"; 633 clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C6_IPCLK>; 634 635 status = "disabled"; 636 }; 637 638 pinctrl_top: pinctrl@139b0000 { 639 compatible = "samsung,exynos7870-pinctrl"; 640 reg = <0x139b0000 0x1000>; 641 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 642 }; 643 644 pinctrl_nfc: pinctrl@139c0000 { 645 compatible = "samsung,exynos7870-pinctrl"; 646 reg = <0x139c0000 0x1000>; 647 interrupts = <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 648 }; 649 650 pinctrl_touch: pinctrl@139d0000 { 651 compatible = "samsung,exynos7870-pinctrl"; 652 reg = <0x139d0000 0x1000>; 653 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 654 }; 655 656 pinctrl_ese: pinctrl@139e0000 { 657 compatible = "samsung,exynos7870-pinctrl"; 658 reg = <0x139e0000 0x1000>; 659 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 662 pinctrl_alive: pinctrl@139f0000 { 663 compatible = "samsung,exynos7870-pinctrl"; 664 reg = <0x139f0000 0x1000>; 665 666 wakeup-interrupt-controller { 667 compatible = "samsung,exynos7870-wakeup-eint", 668 "samsung,exynos7-wakeup-eint"; 669 interrupt-parent = <&gic>; 670 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 671 }; 672 }; 673 674 cmu_isp: clock-controller@144d0000 { 675 compatible = "samsung,exynos7870-cmu-isp"; 676 reg = <0x144d0000 0x1000>; 677 #clock-cells = <1>; 678 679 clock-names = "oscclk", "cam", "isp", "vra"; 680 clocks = <&oscclk>, 681 <&cmu_mif CLK_GOUT_MIF_CMU_ISP_CAM>, 682 <&cmu_mif CLK_GOUT_MIF_CMU_ISP_ISP>, 683 <&cmu_mif CLK_GOUT_MIF_CMU_ISP_VRA>; 684 }; 685 686 syscon_cam0: system-controller@144f1040 { 687 compatible = "samsung,exynos7870-cam0-sysreg", "syscon"; 688 reg = <0x144f1040 0x04>; 689 }; 690 691 dsi: dsi@14800000 { 692 compatible = "samsung,exynos7870-mipi-dsi"; 693 reg = <0x14800000 0x100>; 694 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 695 696 clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_BUS_DISP>, 697 <&cmu_dispaud CLK_GOUT_DISPAUD_APB_DISP>, 698 <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER>, 699 <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER>; 700 clock-names = "bus", "pll", "byte", "esc"; 701 702 phys = <&mipi_phy 1>; 703 phy-names = "dsim"; 704 705 status = "disabled"; 706 707 ports { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 711 port@0 { 712 reg = <0>; 713 714 dsi_to_decon: endpoint { 715 remote-endpoint = <&decon_to_dsi>; 716 }; 717 }; 718 }; 719 }; 720 721 decon: display-controller@14830000 { 722 compatible = "samsung,exynos7870-decon"; 723 reg = <0x14830000 0x8000>; 724 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 727 interrupt-names = "fifo", "vsync", "lcd_sys"; 728 729 clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_PLL>, 730 <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_BUS_USER>, 731 <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_DECON_ECLK>, 732 <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_DECON_VCLK>; 733 clock-names = "pclk_decon0", "aclk_decon0", 734 "decon0_eclk", "decon0_vclk"; 735 736 iommus = <&sysmmu_decon>; 737 738 status = "disabled"; 739 740 port { 741 decon_to_dsi: endpoint { 742 remote-endpoint = <&dsi_to_decon>; 743 }; 744 }; 745 }; 746 747 sysmmu_decon: iommu@14860000 { 748 compatible = "samsung,exynos-sysmmu"; 749 reg = <0x14860000 0x1000>; 750 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 751 #iommu-cells = <0>; 752 753 clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_BUS_USER>; 754 clock-names = "sysmmu"; 755 }; 756 757 pinctrl_dispaud: pinctrl@148c0000 { 758 compatible = "samsung,exynos7870-pinctrl"; 759 reg = <0x148c0000 0x1000>; 760 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 cmu_dispaud: clock-controller@148d0000 { 764 compatible = "samsung,exynos7870-cmu-dispaud"; 765 reg = <0x148d0000 0x1000>; 766 #clock-cells = <1>; 767 768 clock-names = "oscclk", "bus", "decon_eclk", "decon_vclk"; 769 clocks = <&oscclk>, 770 <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_BUS>, 771 <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK>, 772 <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK>; 773 }; 774 775 syscon_disp: system-controller@148f100c { 776 compatible = "samsung,exynos7870-disp-sysreg", "syscon"; 777 reg = <0x148f100c 0x04>; 778 }; 779 }; 780 781 timer { 782 compatible = "arm,armv8-timer"; 783 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 784 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 785 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 786 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 787 788 /* 789 * Non-updatable, broken stock Samsung bootloader does not 790 * configure CNTFRQ_EL0 791 */ 792 clock-frequency = <26000000>; 793 }; 794}; 795 796#include "exynos7870-pinctrl.dtsi" 797#include "arm/samsung/exynos-syscon-restart.dtsi" 798