/freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
H A D | jh7100.dtsi | 188 clocks = <&clkgen JH7100_CLK_SDIO0_AHB>, 189 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>; 201 clocks = <&clkgen JH7100_CLK_SDIO1_AHB>, 202 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>; 214 clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, 215 <&clkgen JH7100_CLK_GMAC_AHB>, 216 <&clkgen JH7100_CLK_GMAC_PTP_REF>, 217 <&clkgen JH7100_CLK_GMAC_TX_INV>, 218 <&clkgen JH7100_CLK_GMAC_GTX>; 242 clkgen: clock-controller@11800000 { label [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/st/ |
H A D | st,clkgen-pll.txt | 7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt 12 "st,clkgen-pll0" 13 "st,clkgen-pll0-a0" 14 "st,clkgen-pll0-c0" 15 "st,clkgen-pll1" 16 "st,clkgen-pll1-c0" 17 "st,stih407-clkgen-plla9" 18 "st,stih418-clkgen-plla9" 29 compatible = "st,clkgen-c32"; 34 compatible = "st,stih407-clkgen-plla9";
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H A D | st,clkgen.txt | 34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt 35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt 46 compatible = "st,clkgen-c32"; 51 compatible = "st,clkgen-pll0";
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H A D | st,clkgen-mux.txt | 13 "st,stih407-clkgen-a9-mux" 25 compatible = "st,stih407-clkgen-a9-mux";
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/freebsd/sys/contrib/device-tree/src/arm/st/ |
H A D | stih410-clock.dtsi | 34 compatible = "st,clkgen-c32"; 39 compatible = "st,stih407-clkgen-plla9"; 49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; 70 compatible = "st,clkgen-c32"; 75 compatible = "st,clkgen-pll0-a0"; 91 compatible = "st,clkgen-c32"; 96 compatible = "st,clkgen-pll0-c0"; 103 compatible = "st,clkgen-pll1-c0"; 145 compatible = "st,clkgen-c32"; 168 compatible = "st,clkgen-c32"; [all …]
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H A D | stih418-clock.dtsi | 34 compatible = "st,clkgen-c32"; 39 compatible = "st,stih418-clkgen-plla9"; 49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; 70 compatible = "st,clkgen-c32"; 75 compatible = "st,clkgen-pll0-a0"; 91 compatible = "st,clkgen-c32"; 96 compatible = "st,clkgen-pll0-c0"; 103 compatible = "st,clkgen-pll1-c0"; 145 compatible = "st,clkgen-c32"; 168 compatible = "st,clkgen-c32"; [all …]
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H A D | stih407-clock.dtsi | 31 compatible = "st,clkgen-c32"; 36 compatible = "st,stih407-clkgen-plla9"; 43 compatible = "st,stih407-clkgen-a9-mux"; 65 compatible = "st,clkgen-c32"; 70 compatible = "st,clkgen-pll0-a0"; 86 compatible = "st,clkgen-c32"; 91 compatible = "st,clkgen-pll0-c0"; 98 compatible = "st,clkgen-pll1-c0"; 140 compatible = "st,clkgen-c32"; 163 compatible = "st,clkgen-c32"; [all …]
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H A D | stih418-b2199.dts | 103 st,tx-retime-src = "clkgen";
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H A D | stih418-b2264.dts | 109 st,tx-retime-src = "clkgen";
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H A D | stihxxx-b2120.dtsi | 147 st,tx-retime-src = "clkgen";
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/freebsd/sys/contrib/device-tree/src/riscv/sophgo/ |
H A D | sg2042.dtsi | 7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h> 55 clocks = <&clkgen GATE_CLK_APB_I2C>; 68 clocks = <&clkgen GATE_CLK_APB_I2C>; 81 clocks = <&clkgen GATE_CLK_APB_I2C>; 94 clocks = <&clkgen GATE_CLK_APB_I2C>; 107 clocks = <&clkgen GATE_CLK_APB_GPIO>, 108 <&clkgen GATE_CLK_GPIO_DB>; 129 clocks = <&clkgen GATE_CLK_APB_GPIO>, 130 <&clkgen GATE_CLK_GPIO_DB>; 151 clocks = <&clkgen GATE_CLK_APB_GPIO>, [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | axi-clkgen.txt | 1 Binding for the axi-clkgen clock generator 8 - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a". 10 - reg : Address and length of the axi-clkgen register set. 21 compatible = "adi,axi-clkgen";
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H A D | adi,axi-clkgen.yaml | 4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml# 7 title: Analog Devices AXI clkgen pcore clock generator 22 - adi,axi-clkgen-2.00.a 23 - adi,zynqmp-axi-clkgen-2.00.a 50 compatible = "adi,axi-clkgen-2.00.a";
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H A D | tango4-clock.txt | 9 - compatible: should be "sigma,tango4-clkgen". 17 clkgen: clkgen@10000 { 18 compatible = "sigma,tango4-clkgen";
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H A D | sophgo,sg2042-clkgen.yaml | 4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml# 14 const: sophgo,sg2042-clkgen 36 See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices. 50 compatible = "sophgo,sg2042-clkgen";
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H A D | nvidia,tegra20-car.yaml | 15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. 17 CLKGEN provides the registers to program the PLLs. It controls most of 20 CLKGEN input signals include the external clock for the reference frequency 23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
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H A D | nvidia,tegra124-car.yaml | 15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. 17 CLKGEN provides the registers to program the PLLs. It controls most of 20 CLKGEN input signals include the external clock for the reference frequency 23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
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H A D | starfive,jh7100-audclk.yaml | 52 clocks = <&clkgen JH7100_CLK_AUDIO_SRC>, 53 <&clkgen JH7100_CLK_AUDIO_12288>, 54 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
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H A D | starfive,jh7100-clkgen.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# 15 const: starfive,jh7100-clkgen 51 compatible = "starfive,jh7100-clkgen";
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H A D | sophgo,sg2042-rpgate.yaml | 46 clocks = <&clkgen 85>;
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/freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
H A D | starfive,jh71x0-temp.yaml | 63 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, 64 <&clkgen JH7100_CLK_TEMP_APB>;
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/freebsd/sys/contrib/device-tree/Bindings/pwm/ |
H A D | opencores,pwm.yaml | 53 clocks = <&clkgen 181>;
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/freebsd/sys/contrib/device-tree/Bindings/mtd/ |
H A D | tango-nand.txt | 23 clocks = <&clkgen SYS_CLK>;
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | starfive,jh7100-pinctrl.yaml | 179 clocks = <&clkgen JH7100_CLK_GPIO_APB>; 180 resets = <&clkgen JH7100_RSTN_GPIO_APB>;
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | sti-dwmac.txt | 24 possible values from "txclk", "clk_125" or "clkgen".
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