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/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,clkgen-pll.txt7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
17 "st,stih407-clkgen-plla9"
18 "st,stih418-clkgen-plla9"
29 compatible = "st,clkgen-c32";
34 compatible = "st,stih407-clkgen-plla9";
H A Dst,clkgen.txt34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
46 compatible = "st,clkgen-c32";
51 compatible = "st,clkgen-pll0";
H A Dst,clkgen-mux.txt13 "st,stih407-clkgen-a9-mux"
25 compatible = "st,stih407-clkgen-a9-mux";
H A Dst,flexgen.txt57 [1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi184 clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
185 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
197 clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
198 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
207 clkgen: clock-controller@11800000 {
208 compatible = "starfive,jh7100-clkgen";
224 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
225 <&clkgen JH7100_CLK_I2C0_APB>;
237 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
238 <&clkgen JH7100_CLK_I2C1_AP
136 clkgen: clock-controller@11800000 { global() label
[all...]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih410-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih407-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
H A Dstih418-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih418-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
H A Dstih407-clock.dtsi31 compatible = "st,clkgen-c32";
36 compatible = "st,stih407-clkgen-plla9";
43 compatible = "st,stih407-clkgen-a9-mux";
65 compatible = "st,clkgen-c32";
70 compatible = "st,clkgen-pll0-a0";
86 compatible = "st,clkgen-c32";
91 compatible = "st,clkgen-pll0-c0";
98 compatible = "st,clkgen-pll1-c0";
140 compatible = "st,clkgen-c32";
163 compatible = "st,clkgen-c32";
[all …]
H A Dstih418-b2199.dts103 st,tx-retime-src = "clkgen";
H A Dstih418-b2264.dts109 st,tx-retime-src = "clkgen";
H A Dstihxxx-b2120.dtsi147 st,tx-retime-src = "clkgen";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Daxi-clkgen.txt1 Binding for the axi-clkgen clock generator
8 - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
10 - reg : Address and length of the axi-clkgen register set.
21 compatible = "adi,axi-clkgen";
H A Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
50 compatible = "adi,axi-clkgen-2.00.a";
H A Dtango4-clock.txt9 - compatible: should be "sigma,tango4-clkgen".
17 clkgen: clkgen@10000 {
18 compatible = "sigma,tango4-clkgen";
H A Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dstarfive,jh7100-audclk.yaml52 clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
53 <&clkgen JH7100_CLK_AUDIO_12288>,
54 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
H A Dstarfive,jh7100-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
15 const: starfive,jh7100-clkgen
51 compatible = "starfive,jh7100-clkgen";
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dstarfive,jh71x0-temp.yaml63 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
64 <&clkgen JH7100_CLK_TEMP_APB>;
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dtango-nand.txt23 clocks = <&clkgen SYS_CLK>;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dstarfive,jh7100-pinctrl.yaml179 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
180 resets = <&clkgen JH7100_RSTN_GPIO_APB>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsti-dwmac.txt24 possible values from "txclk", "clk_125" or "clkgen".
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h99 /** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */
448 /** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-zii-ultra.dtsi458 cs2000: clkgen@4e {
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d-zii-rpu2.dts451 cs2000: clkgen@4e {

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