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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
32 - nvidia,tegra186-mc
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-dai-tdm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "mt8183-afe-clk.h"
11 #include "mt8183-afe-common.h"
12 #include "mt8183-interconnection.h"
13 #include "mt8183-reg.h"
28 TDM_OUT_I2S = 0,
33 TDM_BCK_NON_INV = 0,
38 TDM_LCK_NON_INV = 0,
48 TDM_CHANNEL_BCK_16 = 0,
54 TDM_CHANNEL_NUM_2 = 0,
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-dai-tdm.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "mt8192-afe-clk.h"
12 #include "mt8192-afe-common.h"
13 #include "mt8192-afe-gpio.h"
14 #include "mt8192-interconnection.h"
30 TDM_OUT_I2S = 0,
36 TDM_BCK_NON_INV = 0,
41 TDM_LCK_NON_INV = 0,
51 TDM_CHANNEL_BCK_16 = 0,
57 TDM_CHANNEL_NUM_2 = 0,
[all …]
/linux/tools/perf/tests/
H A Dapi-io.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #define TEMPL "/tmp/perf-test-XXXXXX"
24 ret = -1; \
26 } while (0)
33 ret = -1; \
35 } while (0)
44 if (fd < 0) { in make_test_file()
46 return -1; in make_test_file()
52 return -1; in make_test_file()
55 return 0; in make_test_file()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dst,sta32x.txt7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
H A Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
[all …]
H A Daudio-iio-aux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-iio-aux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 - $ref: dai-common.yaml#
20 const: audio-iio-aux
22 io-channels:
26 io-channel-names:
28 Industrial I/O channel names related to io-channels.
[all …]
/linux/sound/soc/codecs/
H A Dpeb2466.c1 // SPDX-License-Identifier: GPL-2.0
3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver
29 #define PEB2466_TLV_SIZE ARRAY_SIZE(((unsigned int[]){TLV_DB_SCALE_ITEM(0, 0, 0)}))
42 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
43 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
68 #define PEB2466_CMD_W (0 << 5)
70 #define PEB2466_CMD_MASK 0x18
71 #define PEB2466_CMD_XOP 0x18 /* XOP is 0bxxx11xxx */
72 #define PEB2466_CMD_SOP 0x10 /* SOP is 0bxxx10xxx */
73 #define PEB2466_CMD_COP 0x00 /* COP is 0bxxx0xxxx, handle 0bxxx00xxx */
[all …]
H A Dsta350.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
34 #include <sound/soc-dapm.h>
54 /* Power-up register defaults */
56 { 0x0, 0x63 },
57 { 0x1, 0x80 },
58 { 0x2, 0xdf },
59 { 0x3, 0x40 },
60 { 0x4, 0xc2 },
61 { 0x5, 0x5c },
[all …]
H A Dsta32x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
34 #include <sound/soc-dapm.h>
54 /* Power-up register defaults */
56 { 0x0, 0x63 },
57 { 0x1, 0x80 },
58 { 0x2, 0xc2 },
59 { 0x3, 0x40 },
60 { 0x4, 0xc2 },
61 { 0x5, 0x5c },
[all …]
H A Dtlv320adcx140.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
40 "ti,gpo-config-1",
41 "ti,gpo-config-2",
42 "ti,gpo-config-3",
43 "ti,gpo-config-4",
47 { ADCX140_PAGE_SELECT, 0x00 },
48 { ADCX140_SW_RESET, 0x00 },
49 { ADCX140_SLEEP_CFG, 0x00 },
50 { ADCX140_SHDN_CFG, 0x05 },
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Drenesas,rz-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
15 - items:
16 - enum:
17 - renesas,r7s72100-dmac # RZ/A1H
18 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
19 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
[all …]
/linux/drivers/iio/adc/
H A Dintel_mrfld_adc.c1 // SPDX-License-Identifier: GPL-2.0
30 #define BCOVE_GPADCREQ 0xDC
31 #define BCOVE_GPADCREQ_BUSY BIT(0)
67 complete(&adc->completion); in mrfld_adc_thread_isr()
76 struct regmap *regmap = adc->regmap; in mrfld_adc_single_conv()
82 reinit_completion(&adc->completion); in mrfld_adc_single_conv()
93 req = mrfld_adc_requests[chan->channel]; in mrfld_adc_single_conv()
98 time_left = wait_for_completion_interruptible_timeout(&adc->completion, in mrfld_adc_single_conv()
100 if (time_left < 0) { in mrfld_adc_single_conv()
104 if (time_left == 0) { in mrfld_adc_single_conv()
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stmpe-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stmpe-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
20 const: st,stmpe-adc
22 st,norequest-mask:
28 "#io-channel-cells":
32 - compatible
37 - |
[all …]
H A Dti,ads7924.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
25 vref-supply:
29 reset-gpios:
35 "#address-cells":
38 "#size-cells":
39 const: 0
41 "#io-channel-cells":
[all …]
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,quadfs.txt10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible : shall be:
15 "st,quadfs-d0"
16 "st,quadfs-d2"
17 "st,quadfs-d3"
18 "st,quadfs-pll"
21 - #clock-cells : from common clock binding; shall be set to 1.
23 - reg : A Base address and length of the register set.
25 - clocks : from common clock binding
27 - clock-output-names : From common clock binding. The block has 4
[all …]
/linux/Documentation/devicetree/bindings/leds/backlight/
H A Dmediatek,mt6370-backlight.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/mediatek,mt6370-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiaEn Wu <chiaen_wu@richtek.com>
21 - $ref: common.yaml#
26 - mediatek,mt6370-backlight
27 - mediatek,mt6372-backlight
29 default-brightness:
30 minimum: 0
[all …]
/linux/drivers/clk/st/
H A Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
26 #define PLL_BW_GOODREF (0L)
88 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
89 CLKGEN_FIELD(0x2f0, 0x1, 1),
90 CLKGEN_FIELD(0x2f0, 0x1, 2),
91 CLKGEN_FIELD(0x2f0, 0x1, 3) },
92 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
93 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
94 CLKGEN_FIELD(0x2f0, 0x1, 9),
[all …]
/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-etdm.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "mt8195-afe-clk.h"
15 #include "mt8195-afe-common.h"
16 #include "mt8195-reg.h"
24 MTK_DAI_ETDM_FORMAT_I2S = 0,
33 MTK_DAI_ETDM_DATA_ONE_PIN = 0,
61 COWORK_ETDM_NONE = 0,
117 int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id
123 { .rate = 8000, .reg_value = 0, },
176 for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++) in get_etdm_fs_timing()
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 * The external audio clocks are configured as 0 Hz fixed frequency
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
[all …]
/linux/include/linux/iio/frequency/
H A Dad9523.h1 /* SPDX-License-Identifier: GPL-2.0-only */
38 * struct ad9523_channel_spec - Output channel configuration
42 * @sync_ignore_en: Ignore chip-level SYNC signal.
47 * @divider_phase: Divider initial phase after a SYNC. Range 0..63
49 * @channel_divider: 10-bit channel divider.
58 /* CH0..CH3 VCXO, CH4..CH9 VCO2 */
106 * struct ad9523_platform_data - platform specific information
109 * @refa_diff_rcv_en: REFA differential/single-ended input selection.
110 * @refb_diff_rcv_en: REFB differential/single-ended input selection.
111 * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
[all …]
/linux/include/linux/mfd/
H A Dmxs-lradc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Freescale MXS Low Resolution Analog-to-Digital Converter driver
24 #define LRADC_CTRL0 0x00
51 #define LRADC_CTRL1 0x10
54 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
55 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
59 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
60 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
61 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
63 #define LRADC_CTRL2 0x20
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a77470.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
11 #include <dt-bindings/power/r8a77470-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu0: cpu@0 {
[all …]

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