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/linux/arch/mips/kernel/
H A Dsmp-bmips.c521 void __iomem *cbr = bmips_cbr_addr; in bmips_set_reset_vec() local
524 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); in bmips_set_reset_vec()
528 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); in bmips_set_reset_vec()
594 void __iomem __maybe_unused *cbr = bmips_cbr_addr; in bmips_cpu_setup() local
611 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
612 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
613 __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
615 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
616 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
617 __raw_readl(cbr + BMIPS_RAC_CONFIG); in bmips_cpu_setup()
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/linux/tools/perf/scripts/python/
H A Dexport-to-sqlite.py284 do_query(query, 'CREATE TABLE cbr ('
286 'cbr integer,'
463 'cbr.id,'
466 'cbr,'
469 ' FROM cbr'
470 ' INNER JOIN samples ON samples.id = cbr.id')
524 …'CASE WHEN selected_events.name=\'cbr\' THEN (SELECT cbr FROM cbr WHERE cbr.id = samples.id) ELSE …
525 …'CASE WHEN selected_events.name=\'cbr\' THEN (SELECT mhz FROM cbr WHERE cbr.id = samples.id) ELSE …
526 …'CASE WHEN selected_events.name=\'cbr\' THEN (SELECT percent FROM cbr WHERE cbr.id = samples.id) E…
545 ' WHERE selected_events.name IN (\'cbr\',\'mwait\',\'exstop\',\'pwre\',\'pwrx\')')
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H A Dexport-to-postgresql.py460 do_query(query, 'CREATE TABLE cbr ('
462 'cbr integer,'
625 'cbr.id,'
628 'cbr,'
631 ' FROM cbr'
632 ' INNER JOIN samples ON samples.id = cbr.id')
686 'FORMAT(\'%6s\', cbr.cbr) AS cbr,'
687 'FORMAT(\'%6s\', cbr.mhz) AS MHz,'
688 'FORMAT(\'%5s\', cbr.percent) AS percent,'
703 ' FROM cbr'
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H A Dintel-pt-events.py153 cbr = data[0]
155 p = ((cbr * 1000 / data[2]) + 5) / 10
156 print("%3u freq: %4u MHz (%3u%%)" % (cbr, f, p), end=' ')
378 elif name == "cbr":
/linux/arch/mips/bmips/
H A Dsetup.c38 * CBR addr doesn't change and we can cache it.
39 * For broken SoC/Bootloader CBR addr might also be provided via DT
40 * with "brcm,bmips-cbr-reg" in the "cpus" node.
154 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
227 /* Check if DT provide a CBR address */ in device_tree_init()
228 if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) in device_tree_init()
231 /* Make sure CBR address is outside DRAM window */ in device_tree_init()
234 WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", in device_tree_init()
240 /* Since CBR is provided by DT, enable RAC flush */ in device_tree_init()
H A Ddma.c12 void __iomem *cbr = bmips_cbr_addr; in arch_sync_dma_for_cpu_all() local
24 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); in arch_sync_dma_for_cpu_all()
25 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); in arch_sync_dma_for_cpu_all()
26 __raw_readl(cbr + BMIPS_RAC_CONFIG); in arch_sync_dma_for_cpu_all()
/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.yaml58 brcm,bmips-cbr-reg:
59 description: Reference address of the CBR.
60 Some SoC suffer from a BUG where CBR(Core Base Register)
64 The CBR address is always the same on the SoC hence it
89 - brcm,bmips-cbr-reg
/linux/arch/mips/bcm63xx/
H A Dsetup.c27 * CBR addr doesn't change and we can cache it.
28 * For broken SoC/Bootloader CBR addr might also be provided via DT
29 * with "brcm,bmips-cbr-reg" in the "cpus" node.
H A Dprom.c25 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
/linux/tools/perf/util/intel-pt-decoder/
H A Dintel-pt-decoder.c188 unsigned int cbr; member
775 unsigned int cbr; member
813 unsigned int cbr; in intel_pt_calc_cyc_cb() local
933 cbr = pkt_info->packet.payload; in intel_pt_calc_cyc_cb()
934 if (data->cbr && data->cbr != cbr) in intel_pt_calc_cyc_cb()
936 data->cbr = cbr; in intel_pt_calc_cyc_cb()
937 data->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr; in intel_pt_calc_cyc_cb()
1992 unsigned int cbr = decoder->packet.payload & 0xff; intel_pt_calc_cbr() local
[all...]
H A Dintel-pt-decoder.h249 uint32_t cbr; member
H A Dintel-pt-pkt-decoder.c47 [INTEL_PT_CBR] = "CBR",
364 case 0x03: /* CBR */ in intel_pt_get_ext()
/linux/arch/mips/bcm47xx/
H A Dsetup.c50 * CBR addr doesn't change and we can cache it.
51 * For broken SoC/Bootloader CBR addr might also be provided via DT
52 * with "brcm,bmips-cbr-reg" in the "cpus" node.
H A Dprom.c114 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
/linux/drivers/misc/sgi-gru/
H A Dgrutables.h365 unsigned char ts_cbr_au_count;/* Number of CBR resources
371 signed char ts_cbr_idx[GRU_CBR_AU];/* CBR numbers of each
491 #define CBR_BYTES(cbr) ((cbr) * GRU_HANDLE_BYTES * GRU_CBR_AU_SIZE * 2) argument
523 /* Scan each CBR whose bit is set in a TFM (or copy of) */
527 /* Scan each CBR in a CBR bitmap. Note: multiple CBRs in an allocation unit */
H A Dgrukservices.h16 * Processes SENDING messages will use a kernel CBR/DSR to send
188 * cb - pointer to first CBR
H A Dgruprocfs.c193 seq_puts(file, "# gid nid ctx cbr dsr ctx cbr dsr\n"); in gru_seq_show()
H A Dgrukservices.c269 * Free the current cpus reserved DSR/CBR resources.
354 * cb - pointer to first CBR
964 printk(KERN_DEBUG "GRU:%d quicktest0: CBR failure 1\n", smp_processor_id()); in quicktest0()
974 printk(KERN_DEBUG "GRU:%d quicktest0: CBR failure 2\n", smp_processor_id()); in quicktest0()
1091 gen->istatus = CBS_CALL_OS; /* don't handle this CBR again */ in quicktest2()
H A Dgrufault.c348 * cb Address of user CBR. Null if not running in user context
456 /* Atomic failure switch CBR to UPM */ in gru_try_dropin()
493 /* All errors (atomic & non-atomic) switch CBR to EXCEPTION state */ in gru_try_dropin()
/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h187 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
325 #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
326 #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
425 #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
426 #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
588 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
590 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
626 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
627 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
[all …]
H A Ddma.c705 /* A queue got CBR overrun */ in ath5k_hw_get_isr()
709 /* A queue got CBR underrun */ in ath5k_hw_get_isr()
/linux/arch/mips/include/asm/
H A Dbmips.h19 /* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
/linux/arch/sh/kernel/cpu/sh4a/
H A Dubc.c27 /* CBR */
/linux/include/uapi/linux/
H A Datm.h45 #define ATM_AAL1 1 /* AAL1 (CBR) */
/linux/drivers/staging/media/deprecated/atmel/
H A Datmel-isc-regs.h240 /* Color Space Conversion CBR CBG Register */

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