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/linux/arch/arm/mm/
H A Dproc-arm1020.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
149 mcr p15, 0, ip, c7, c10, 4 @ drain WB
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
159 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dproc-arm926.S72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
73 mcr p15, 0, ip, c7, c10, 4 @ drain WB
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
137 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
141 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
142 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dproc-mohawk.S65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
120 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
142 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
[all …]
H A Dproc-arm925.S112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
113 mcr p15, 0, ip, c7, c10, 4 @ drain WB
115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
135 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
169 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
173 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
178 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
179 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
99 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
H A Dproc-arm946.S63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
113 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
120 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
121 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
H A Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
143 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
150 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
H A Dproc-arm920.S80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
81 mcr p15, 0, ip, c7, c10, 4 @ drain WB
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
H A Dproc-arm922.S82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
143 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
163 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
165 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
H A Dproc-feroceon.S75 mcr p15, 0, r0, c7, c10, 4 @ drain WB
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
119 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
165 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dproc-fa526.S61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
62 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
90 mcr p15, 0, r0, c7, c10, 4 @ drain WB
108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
114 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
H A Dproc-xsc3.S69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
[all …]
H A Dproc-arm1022.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-arm1026.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-arm1020e.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
179 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
H A Dproc-xscale.S92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
159 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
219 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
[all …]
H A Dproc-arm940.S56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
126 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
[all …]
H A Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
118 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
124 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
172 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dcopypage-feroceon.c29 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
33 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
37 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
41 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
45 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
49 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
53 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
57 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
60 mcr p15, 0, %2, c7, c10, 4 @ drain WB" in feroceon_copy_user_page()
94 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_clear_user_highpage()
[all …]
H A Dproc-sa1100.S76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
131 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
154 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
171 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
172 mcr p15, 0, r0, c7, c10, 4 @ drain WB
192 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
193 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
H A Dproc-v6.S66 mcr p15, 0, r1, c7, c5, 4 @ ISB
80 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
162 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
163 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
164 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
165 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
[all …]
H A Dproc-arm720.S73 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
145 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
147 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
H A Dproc-sa110.S68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
121 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
160 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
161 mcr p15, 0, r0, c7, c10, 4 @ drain WB
169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
170 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
/linux/arch/arm/include/asm/hardware/
H A Dcp14.h49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
64 #define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
80 #define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
96 #define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
112 #define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
129 #define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
144 #define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
145 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
146 #define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
147 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
[all …]
/linux/arch/arm/boot/compressed/
H A Dhead.S731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
732 mcr p15, 0, r0, c6, c7, 1
744 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
761 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
[all …]

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