Lines Matching full:c7
69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
206 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
207 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
208 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
233 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
239 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
240 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
255 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
260 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
261 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
262 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
280 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
282 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
287 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
300 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
304 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
317 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
321 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
369 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
370 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
371 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
439 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
440 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
441 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
442 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
459 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
460 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
461 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
462 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs