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Searched full:c0 (Results 1 – 25 of 655) sorted by relevance

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/linux/arch/arm/include/asm/hardware/
H A D	cp14.h	`45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0) 46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0) 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0) 48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0) 49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0) 50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0) 51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0) 52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0) 53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2) 54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2) [all …]`
/linux/tools/testing/selftests/hid/tests/
H A D	test_multitouch.py	492 …c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00 92 02 01 c0 05… 1112 …c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 01 c0 c0 05 0d 09 0e a1 01 85 11 09 23 a1 02 09 52 09… 1123 …c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 03 c0 c0 05 0d 09 0e a1 01 85 11 09 23 a1 02 09 52 09… 1134 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08… 1171 …c0 09 22 a1 02 05 0d 35 00 45 00 55 00 65 00 09 42 25 01 75 01 81 02 09 32 81 02 09 47 81 02 75 05… 1181 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08… 1190 …6 0a 26 ff 0f 09 30 81 02 46 b2 05 26 ff 0f 09 31 81 02 05 0d 75 08 85 02 09 55 25 10 b1 02 c0 c0", 1199 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… 1208 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08… 1217 …c0 05 01 09 02 a1 01 09 01 a1 00 85 01 05 09 19 01 29 03 15 00 25 01 95 03 75 01 81 02 95 01 75 05… [all …]
H A D	test_tablet.py	1302 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1310 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1318 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1326 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1334 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1342 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1350 …c0 c0 05 0d 09 04 a1 01 85 30 09 22 a1 02 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81… 1358 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… 1367 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… 1376 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… [all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A D	g98.fuc0s	`514 cxsin $c0 515 cxsout $c0 525 cxsin $c0 526 cenc $c0 $c0 527 cxsout $c0 533 cxsin $c0 534 cdec $c0 $c0 535 cxsout $c0 540 cxsin $c0 541 cxor $c6 $c0 [all …]`
/linux/arch/arm/mm/
H A D	proc-v7.S	`35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 38 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 139 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 142 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 146 mrc p15, 0, r7, c2, c0, 1 @ TTB 1 148 mrc p15, 0, r11, c2, c0, 2 @ TTB control register 150 mrc p15, 0, r8, c1, c0, 0 @ Control register [all …]`
H A D	proc-v6.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 113 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 118 mcr p15, 0, r1, c13, c0, 1 @ set context ID 148 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 150 mrc p15, 0, r5, c3, c0, 0 @ Domain ID [all …]`
H A D	proc-sa1100.S	`43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 mcr p15, 0, r0, c1, c0, 0 @ disable caches 81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 153 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 182 mrc p15, 0, r4, c3, c0, 0 @ domain ID 183 mrc p15, 0, r5, c13, c0, 0 @ PID 184 mrc p15, 0, r6, c1, c0, 0 @ control reg [all …]`
H A D	proc-arm740.S	`48 mrc p15, 0, r0, c1, c0, 0 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 83 mcr p15, 0, r0, c6, c0 @ set area 0, default 109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable 115 mcr p15, 0, r0, c3, c0 119 mcr p15, 0, r0, c5, c0 @ all read/write access [all …]`
H A D	proc-xsc3.S	`57 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 425 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 427 mrc p15, 0, r6, c13, c0, 0 @ PID [all …]`
H A D	proc-mohawk.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 327 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 353 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 355 mrc p15, 0, r6, c13, c0, 0 @ PID 356 mrc p15, 0, r7, c3, c0, 0 @ domain ID 357 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg [all …]`
H A D	cache-v7.S	44 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR 46 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR 69 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR 101 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 107 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register 129 mrc p15, 1, r0, c0, c0, 1 @ read clidr 144 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 146 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 180 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
/linux/tools/testing/selftests/cgroup/
H A D	test_cpuset_prs.sh	`198 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1" 199 " C0-1 . . C2-3 P1 . . . 0 " 200 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 " 201 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 " 202 " C0-1:S+ . . C2-3 . . . P1 0 " 203 " C0-1:P1 . . C2-3 S+ C1 . . 0 " 204 " C0-1:P1 . . C2-3 S+ C1:P1 . . 0 " 205 " C0-1:P1 . . C2-3 S+ C1:P1 . P1 0 " 206 " C0-1:P1 . . C2-3 C4-5 . . . 0 A1:4-5" 207 " C0-1:P1 . . C2-3 S+:C4-5 . . . 0 A1:4-5" [all …]`
/linux/arch/arm/include/debug/
H A D	icedcc.S	`16 mcr p14, 0, \rd, c0, c5, 0 21 mrc p14, 0, \rx, c0, c1, 0 34 mrc p14, 0, \rx, c0, c1, 0 43 mcr p14, 0, \rd, c8, c0, 0 48 mrc p14, 0, \rx, c14, c0, 0 61 mrc p14, 0, \rx, c14, c0, 0 70 mcr p14, 0, \rd, c1, c0, 0 75 mrc p14, 0, \rx, c0, c0, 0 89 mrc p14, 0, \rx, c0, c0, 0`
/linux/arch/s390/crypto/
H A D	chacha-s390.S	`442 #define C0 %v2 macro 514 VLR C0,K2 545 VAF C0,C0,D0 551 VX B0,B0,C0 583 VAF C0,C0,D0 589 VX B0,B0,C0 602 VSLDB C0,C0,C0,8 640 VAF C0,C0,D0 646 VX B0,B0,C0 678 VAF C0,C0,D0 [all …]`
/linux/drivers/gpu/drm/tidss/
H A D	tidss_scale_coefs.c	19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, }, 25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, }, 31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, }, 37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, }, 43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, }, 49 .c0 = { 288, 286, 284, 280, 276, 266, 256, 244, 232, }, 55 .c0 = { 312, 308, 304, 298, 292, 282, 272, 258, 244, }, 61 .c0 = { 336, 332, 328, 320, 312, 300, 288, 272, 256, }, 67 .c0 = { 368, 364, 360, 350, 340, 326, 312, 292, 272, }, 73 .c0 = { 400, 398, 396, 384, 372, 354, 336, 312, 288, }, [all …]
/linux/arch/arm/kernel/
H A D	hyp-stub.S	`116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) 126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR 133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR 137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR 139 mrc p15, 0, r7, c0, c0, 0 @ MIDR 140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR 142 mrc p15, 0, r7, c0, c0, 5 @ MPIDR 143 mcr p15, 4, r7, c0, c0, 5 @ VMPIDR 147 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 166 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 [all …]`
/linux/arch/arm/include/asm/
H A D	uaccess-asm.h	`50 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register 62 mcr p15, 0, \tmp, c3, c0, 0 76 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR 79 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR 90 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR 93 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR 132 DACR( mrc p15, 0, \tmp0, c3, c0, 0) 134 PAN( mrc p15, 0, \tmp0, c2, c0, 2) 139 mcr p15, 0, \tmp2, c3, c0, 0 145 mcr p15, 0, \tmp2, c3, c0, 0 [all …]`
/linux/arch/arm/boot/compressed/
H A D	head.S	`38 mcr p14, 0, \ch, c0, c5, 0 44 mcr p14, 0, \ch, c8, c0, 0 50 mcr p14, 0, \ch, c1, c0, 0 141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR 145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR 696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr 735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission [all …]`
/linux/arch/arm/mach-omap2/
H A D	sleep44xx.S	`88 mrc p15, 0, r0, c1, c0, 0 90 mcr p15, 0, r0, c1, c0, 0 108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 128 mrcne p15, 0, r0, c1, c0, 1 130 mcrne p15, 0, r0, c1, c0, 1 146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR 189 mrc p15, 0, r0, c1, c0, 0 192 mcreq p15, 0, r0, c1, c0, 0 201 mrc p15, 0, r0, c1, c0, 1 [all …]`
/linux/arch/arm/mach-sunxi/
H A D	headsmp.S	`25 mrc p15, 0, r1, c0, c0, 0 37 mrc p15, 1, r1, c15, c0, 4 39 mcr p15, 1, r1, c15, c0, 4 42 mrc p15, 1, r1, c15, c0, 0 47 mcr p15, 1, r1, c15, c0, 0 50 mrc p15, 1, r1, c9, c0, 2 53 mcr p15, 1, r1, c9, c0, 2`
/linux/tools/testing/selftests/net/forwarding/
H A D	bridge_igmp.sh	17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03" 19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c" 21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c" 25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00… 29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e" 33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
/linux/arch/arm/mach-spear/
H A D	hotplug.c	`28 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower() 30 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower() 31 " mrc p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower() 33 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower() 43 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower() 45 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower() 46 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()`
/linux/arch/arm/mach-versatile/
H A D	hotplug.c	30 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower() 32 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower() 33 " mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower() 35 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower() 46 "mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower() 49 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower() 51 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
/linux/Documentation/admin-guide/hw-vuln/
H A D	cross-thread-rsb.rst	9 transitions out of C0 state, the other sibling thread could use return target 10 predictions from the sibling thread that transitioned out of C0. 15 transitioning out of C0. This could result in a guest-controlled return target 41 requests to transition out of the C0 state. This can be communicated with the 42 HLT instruction or with an MWAIT instruction that requests non-C0. 43 When the thread re-enters the C0 state, the processor transitions back 44 to 2T mode, assuming the other thread is also still in C0 state. 62 instructions with targeted return locations and then transitioning out of C0 86 attempts to transition out of C0. A VMM can use the KVM_CAP_X86_DISABLE_EXITS
/linux/arch/arm/mach-tegra/
H A D	sleep.h	`70 mrc p15, 0, \rd, c0, c0, 5 82 mrc p15, 0, \tmp1, c0, c0, 0 90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR 92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR 96 mrceq p15, 0, \tmp1, c0, c0, 5`

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