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/linux/drivers/staging/greybus/
H A Dbootrom.c3 * BOOTROM Greybus driver.
40 struct mutex mutex; /* Protects bootrom->fw */
43 static void free_firmware(struct gb_bootrom *bootrom) in free_firmware() argument
45 if (!bootrom->fw) in free_firmware()
48 release_firmware(bootrom->fw); in free_firmware()
49 bootrom->fw = NULL; in free_firmware()
55 struct gb_bootrom *bootrom = container_of(dwork, in gb_bootrom_timedout() local
57 struct device *dev = &bootrom->connection->bundle->dev; in gb_bootrom_timedout()
60 switch (bootrom->next_request) { in gb_bootrom_timedout()
75 dev_err(dev, "Invalid next-request: %u", bootrom->next_request); in gb_bootrom_timedout()
[all …]
H A DMakefile6 gb-bootrom-y := bootrom.o
18 obj-$(CONFIG_GREYBUS_BOOTROM) += gb-bootrom.o
H A DKconfig27 tristate "Greybus Bootrom Class driver"
30 Greybus Bootrom Class specification.
33 will be called gb-bootrom.ko
/linux/arch/arm/mach-mvebu/
H A Dplatsmp.c131 * the bootROM is mapped at the correct address. in armada_xp_smp_prepare_cpus()
133 node = of_find_compatible_node(NULL, NULL, "marvell,bootrom"); in armada_xp_smp_prepare_cpus()
135 panic("Cannot find 'marvell,bootrom' compatible node"); in armada_xp_smp_prepare_cpus()
140 panic("Cannot get 'bootrom' node address"); in armada_xp_smp_prepare_cpus()
144 panic("The address for the BootROM is incorrect"); in armada_xp_smp_prepare_cpus()
H A Dpmsu.c122 * BootROM Mbus window, and instead remaps a crypto SRAM into which a
123 * custom piece of code is copied to replace the problematic BootROM.
404 * performed by the BootROM software". To avoid this, we in armada_370_cpuidle_init()
405 * replace the restart code of the bootrom by a a simple jump in armada_370_cpuidle_init()
H A Dpmsu_ll.S31 * Disable the MMU that might have been enabled in BootROM if
/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt118 bootrom {
119 compatible = "marvell,bootrom";
160 bootrom {
161 compatible = "marvell,bootrom";
224 bootrom {
225 compatible = "marvell,bootrom";
/linux/arch/mips/ralink/
H A Dbootrom.c21 DEFINE_SHOW_ATTRIBUTE(bootrom);
25 debugfs_create_file("bootrom", 0444, NULL, NULL, &bootrom_fops); in bootrom_setup()
/linux/arch/powerpc/include/asm/
H A Duninorth.h97 * the bootrom, I'm not sure about their exact meaning yet
135 * the bootROM decides whether to boot or to sleep/spinloop depending
140 /* This register appear to be read by the bootROM to decide what
146 /* This last bit appear to be used by the bootROM to know the second
/linux/include/linux/greybus/
H A Dgreybus_protocols.h363 /* Bootrom Protocol */
365 /* Version of the Greybus bootrom protocol we support */
369 /* Greybus bootrom request types */
377 /* Greybus bootrom boot stages */
379 #define GB_BOOTROM_BOOT_STAGE_TWO 0x02 /* Bootrom package to be loaded by the boot ROM */
382 /* Greybus bootrom ready to boot status */
387 /* Max bootrom data fetch size in bytes */
400 /* Bootrom protocol firmware size request/response */
409 /* Bootrom protocol get firmware request/response */
417 /* Bootrom protocol Ready to boot request */
[all …]
/linux/arch/arm/mach-shmobile/
H A Dheadsmp.S65 ldr r0, bootrom
77 bootrom: label
/linux/Documentation/devicetree/bindings/mtd/
H A Dgpmi-nand.yaml79 WARNING: on i.MX28 blockmark swapping cannot be disabled for the BootROM
81 on may not be accessible by the BootROM code.
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-lp-sk-nand.dtso57 ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
96 reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
H A Dk3-am642-evm-nand.dtso82 ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
124 reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi22 bootrom: bootrom@0 { label
/linux/arch/arm/boot/dts/marvell/
H A Darmada-370.dtsi33 bootrom {
34 compatible = "marvell,bootrom";
273 * on the BootROM code to enter/exit idle state).
H A Darmada-xp.dtsi33 bootrom {
34 compatible = "marvell,bootrom";
H A Darmada-xp-98dx3236.dtsi49 bootrom {
50 compatible = "marvell,bootrom";
/linux/drivers/nfc/nfcmrvl/
H A Dfw_dnld.h55 struct nfcmrvl_fw_binary_config bootrom; member
H A Dfw_dnld.c137 nfc_info(priv->dev, "BootROM reset, start fw download\n"); in process_state_reset()
534 /* Ronfigure HI to be sure that it is the bootrom values */ in nfcmrvl_fw_dnld_start()
536 &fw_dnld->header->bootrom.config); in nfcmrvl_fw_dnld_start()
/linux/arch/arm/mach-rockchip/
H A Dplatsmp.c138 * We communicate with the bootrom to active the cpus other in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
/linux/arch/arm/mach-sti/
H A Dplatsmp.c35 * Secondary CPU is initialised and started by a U-BOOTROM firmware. in sti_boot_secondary()
/linux/arch/arm/boot/dts/cirrus/
H A Dep93xx-ts7250.dts56 label = "TS-BOOTROM";
/linux/drivers/gpu/drm/tegra/
H A Driscv.c101 dev_err(riscv->dev, "error during bootrom execution. BR_RETCODE=%d\n", val); in tegra_drm_riscv_boot_bootrom()
/linux/drivers/gpu/drm/xe/
H A Dxe_guc.c990 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_wait_ucode() local
995 …xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, … in guc_wait_ucode()
997 bootrom, ukernel, in guc_wait_ucode()
1001 switch (bootrom) { in guc_wait_ucode()
1061 * HW is fixed for each platform and hard-coded in the bootrom. in __xe_guc_upload()

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