Home
last modified time | relevance | path

Searched full:beats (Results 1 – 25 of 28) sorted by relevance

12

/freebsd/lib/libpmc/
H A Dpmc.cmn-600.3318 Number of RData beats, RVALID and RREADY, dispatched on port 0.
321 Number of RData beats, RVALID and RREADY, dispatched on port 1.
324 Number of RData beats, RVALID and RREADY, dispatched on port 2.
352 Number of WData beats, WVALID and WREADY, dispatched on port 0.
355 Number of WData beats, WVALID and WREADY, dispatched on port 1.
358 Number of WData beats, WVALID and WREADY, dispatched on port 2.
379 Number of RData beats, RVALID and RREADY, dispatched on port 0.
382 Number of RData beats, RVALID and RREADY, dispatched on port 1.
385 Number of RData beats, RVALID and RREADY, dispatched on port 2.
412 Number of WData beats, WVALID and WREADY, dispatched on port 0.
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_s2m.h394 * Defines the maximum number of AXI beats for a single AXI burst. This value is
402 * Defines the maximum number of AXI beats for a single AXI burst. This value is
415 * Defines the maximum number of AXI beats for a single AXI burst. This value is
422 * (AXI beats).
424 * Default value is 2 cache lines, 8 beats.
448 * Maximum number of outstanding data beats for data write to AXI.
449 * (AXI beats).
460 * Maximum number of outstanding data beats for descriptor write to AXI.
461 * (AXI beats).
635 * Maximum number of data beats in the data write FIFO.
[all …]
H A Dal_hal_udma_regs_m2s.h450 * Defines the maximum number of AXI beats for a single AXI burst.
463 * Defines the maximum number of AXI beats for a single AXI burst.
465 * Maximum burst size for reading data( in AXI beats, 128-bits)
466 * (default – 16 beats, 256 bytes)
478 * Defines the maximum number of AXI beats for a single AXI burst.
485 * Defined in AXI beats
488 * Default value is 2 cache lines, 32 descriptors, 8 beats.
508 * Maximum number of outstanding data beats for descriptor write to AXI (AXI
509 * beats)
673 /* Minimum number of beats to start packet transmission. */
[all …]
H A Dal_hal_udma_config.h149 uint16_t data_fifo_depth; /* maximum number of data beats in the
179 uint16_t data_fifo_depth; /* maximum number of data beats in the
284 * (in AXI beats-128b) (5b)
289 uint16_t max_rd_d_out_beats; /* max num. of data read beats (10b) */
H A Dal_hal_udma_config.c1042 /* convert burst size from bytes to beats (16 byte) */ in al_udma_s2m_compl_desc_burst_config()
H A Dal_hal_nb_regs.h1021 Performance optimization feature to chop non-active data beats to the DDR. */
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dbaikal,bt1-ahci.yaml61 transaction size can't exceed 16 beats (AxLEN[3:0]).
68 transaction size can't exceed 16 beats (AxLEN[3:0]).
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a76-n1/
H A Dbus.json8 …e data channels between the core and the SCU. If both read and write data beats are transferred on…
/freebsd/contrib/file/magic/Magdir/
H A Druby36 # Classes with no modules or defs, beats simple ASCII
/freebsd/share/man/man4/
H A Dspkr.4159 Tempo Beats Per Minute
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmvebu-devbus.txt96 inactive (high) between data beats of a burst write.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM55.td31 // Each MVE instruction needs to take 2 beats, each performing 64bits of the
32 // 128bit vector operation. So long as the beats are to different pipelines,
48 // instruction. MVE instruction take two beats, modelled using
H A DARMFeatures.td382 "Model MVE instructions as a 2 beats per tick architecture">;
385 "Model MVE instructions as a 4 beats per tick architecture">;
H A DARMSubtarget.h138 /// The cost factor for MVE instructions, representing the multiple beats an
H A DARMTargetTransformInfo.cpp1059 // for "multiple beats" potentially needed by MVE instructions. in getCmpSelInstrCost()
1444 // for "multiple beats" potentially needed by MVE instructions. in getArithmeticInstrCost()
/freebsd/usr.bin/compress/doc/
H A DNOTES113 beats me, but if sperry got a hold of them on these issues,
/freebsd/crypto/openssl/test/
H A Ddanetest.in1510 # DANE-EE(3) beats DANE-TA(2)
1559 # DANE-TA(2) depth 1 beats DANE-TA(2) depth 2
1608 # DANE-TA(2) depth 2 beats PKIX-TA(0) depth 1
1657 # DANE-TA(2) depth 2 beats PKIX-EE depth 0
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwmac.yaml438 Use Address-Aligned Beats
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsELFObjectWriter.cpp121 LLVM_DEBUG(dbgs() << ".. and it beats the last one\n"); in find_best()
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h1309 /* MAX number of beats for packet parsing */
2192 /* Max number of bus beats for parsing */
2219 /* Max data beats that can be used in the Tx FIFO */
2530 /* MAX number of beats for packet parsing */
/freebsd/usr.sbin/tzsetup/
H A Dtzsetup.c294 * Beats worrying about dynamic allocation.
/freebsd/sys/contrib/ncsw/inc/Peripherals/
H A Dfm_ext.h808 @Description Define DMA AXI number of beats.
809 Calling this routine changes the AXI number of beats in the internal
1091 amount of DATA beats transferred on the AXI READ and WRITE
/freebsd/contrib/arm-optimized-routines/math/tools/
H A Dremez.jl535 # new subsequence that beats the previous record holder in its slot.
/freebsd/lib/libefivar/
H A Defivar-dp-parse.c50 * OK. Now this is evil. Can't typedef it again. Sure beats changing them all.
/freebsd/sys/dev/dc/
H A Dif_dc.c2732 * The performance hit is tremendous, but it beats dropping frames all

12