| /linux/drivers/pinctrl/samsung/ |
| H A D | pinctrl-exynos-arm64.c | 73 /* pin banks of exynos5433 pin-controller - ALIVE */
75 /* Must start with EINTG banks, ordered by EINT group number. */
87 /* pin banks of exynos5433 pin-controller - AUD */
89 /* Must start with EINTG banks, ordered by EINT group number. */
94 /* pin banks of exynos5433 pin-controller - CPIF */
96 /* Must start with EINTG banks, ordered by EINT group number. */
100 /* pin banks of exynos5433 pin-controller - eSE */
102 /* Must start with EINTG banks, ordered by EINT group number. */
106 /* pin banks of exynos5433 pin-controller - FINGER */
108 /* Must start with EINTG banks, ordered by EINT group number. */
[all …]
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| H A D | pinctrl-exynos-arm.c | 103 /* pin banks of s5pv210 pin-controller */
105 /* Must start with EINTG banks, ordered by EINT group number. */
164 /* pin banks of exynos3250 pin-controller 0 */
166 /* Must start with EINTG banks, ordered by EINT group number. */
176 /* pin banks of exynos3250 pin-controller 1 */
178 /* Must start with EINTG banks, ordered by EINT group number. */
198 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
251 /* pin banks of exynos4210 pin-controller 0 */
253 /* Must start with EINTG banks, ordered by EINT group number. */
272 /* pin banks of exynos4210 pin-controller 1 */
[all …]
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| H A D | pinctrl-exynos.h | 192 * @nr_banks: count of banks being part of the mux
193 * @banks: array of banks being part of the mux
197 struct samsung_pin_bank *banks[] __counted_by(nr_banks);
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| /linux/arch/x86/kernel/cpu/mce/ |
| H A D | threshold.c | 46 storm->banks[bank].history = ~0ull; in mce_inherit_storm()
47 storm->banks[bank].timestamp = jiffies; in mce_inherit_storm()
74 storm->banks[bank].in_storm_mode = true; in cmci_storm_begin()
89 storm->banks[bank].history = 0; in cmci_storm_end()
90 storm->banks[bank].in_storm_mode = false; in cmci_storm_end()
92 /* If no banks left in storm mode, stop polling. */ in cmci_storm_end()
104 /* No tracking needed for banks that do not support CMCI */ in mce_track_storm()
105 if (storm->banks[mce->bank].poll_only) in mce_track_storm()
116 if (!storm->banks[mce->bank].in_storm_mode) { in mce_track_storm()
117 delta = now - storm->banks[mce->bank].timestamp; in mce_track_storm()
[all …]
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| H A D | internal.h | 107 * banks: per-cpu, per-bank details
108 * stormy_bank_count: count of MC banks in storm state
112 struct storm_bank banks[MAX_NR_BANKS]; member
209 * banks. Also, to accommodate the new banks and registers, the MCA
217 /* AMD-style error thresholding banks present. */
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| /linux/arch/arm/mach-omap2/ |
| H A D | powerdomains7xx_data.c | 37 .banks = 4,
78 .banks = 2,
92 .banks = 1,
105 .banks = 2,
119 .banks = 1,
132 .banks = 1,
144 .banks = 5,
170 .banks = 1,
186 .banks = 1,
201 .banks = 1,
[all …]
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| H A D | powerdomains44xx_data.c | 38 .banks = 5,
63 .banks = 1,
81 .banks = 2,
101 .banks = 1,
119 .banks = 3,
140 .banks = 1,
157 .banks = 1,
174 .banks = 1,
190 .banks = 1,
207 .banks = 3,
[all …]
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| H A D | powerdomains54xx_data.c | 36 .banks = 5,
62 .banks = 2,
91 .banks = 1,
109 .banks = 1,
126 .banks = 1,
142 .banks = 1,
159 .banks = 2,
188 .banks = 3,
209 .banks = 1,
227 .banks = 2,
[all …]
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| H A D | powerdomains3xxx_data.c | 37 .banks = 4,
59 .banks = 1,
75 .banks = 1,
100 .banks = 2,
122 .banks = 2,
139 .banks = 2,
156 .banks = 1,
171 .banks = 1,
192 .banks = 1,
207 .banks = 1,
[all …]
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| H A D | powerdomains2xxx_data.c | 31 .banks = 1,
46 .banks = 1,
61 .banks = 3,
87 .banks = 1,
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| H A D | powerdomains43xx_data.c | 23 .banks = 1,
37 .banks = 3,
65 .banks = 1,
95 .banks = 4,
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| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-memory.json | 580 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
585 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
749 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
754 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
759 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
764 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
769 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
774 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
779 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
784 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-memory.json | 543 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
548 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
712 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
717 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
722 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
727 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
732 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
737 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
742 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
747 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-memory.json | 572 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
577 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
741 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
746 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
751 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
756 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
761 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
766 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
771 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
776 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
[all …]
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_aca.c | 49 static void aca_banks_init(struct aca_banks *banks) in aca_banks_init() argument
51 if (!banks) in aca_banks_init()
54 memset(banks, 0, sizeof(*banks)); in aca_banks_init()
55 INIT_LIST_HEAD(&banks->list); in aca_banks_init()
58 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) in aca_banks_add_bank() argument
72 list_add_tail(&node->node, &banks->list); in aca_banks_add_bank()
74 banks->nr_banks++; in aca_banks_add_bank()
79 static void aca_banks_release(struct aca_banks *banks) in aca_banks_release() argument
83 if (list_empty(&banks->list)) in aca_banks_release()
86 list_for_each_entry_safe(node, tmp, &banks->list, node) { in aca_banks_release()
[all …]
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| /linux/arch/powerpc/platforms/embedded6xx/ |
| H A D | mpc10x.h | 107 #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */
108 #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */
109 #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */
110 #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */
112 #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */
113 #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */
114 #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */
115 #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-ssbi-gpio.c | 325 u8 banks = 0; in pm8xxx_pin_config_set() local
335 banks |= BIT(2); in pm8xxx_pin_config_set()
337 banks |= BIT(3); in pm8xxx_pin_config_set()
341 banks |= BIT(2); in pm8xxx_pin_config_set()
343 banks |= BIT(3); in pm8xxx_pin_config_set()
354 banks |= BIT(2); in pm8xxx_pin_config_set()
356 banks |= BIT(3); in pm8xxx_pin_config_set()
360 banks |= BIT(3); in pm8xxx_pin_config_set()
364 banks |= BIT(0) | BIT(1); in pm8xxx_pin_config_set()
369 banks |= BIT(0) | BIT(1); in pm8xxx_pin_config_set()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | uncore-memory.json | 643 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
812 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
822 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
832 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
842 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
852 "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
1021 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
1031 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
1041 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
1051 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
[all …]
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| /linux/drivers/memory/ |
| H A D | fsl_ifc.c | 42 * This function walks IFC banks comparing "Base address" field of the CSPR
54 for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) { in fsl_ifc_find()
199 * resources for the NAND banks themselves are allocated
205 int version, banks; in fsl_ifc_ctrl_probe() local
235 banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; in fsl_ifc_ctrl_probe()
236 dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", in fsl_ifc_ctrl_probe()
237 version >> 24, (version >> 16) & 0xf, banks); in fsl_ifc_ctrl_probe()
240 fsl_ifc_ctrl_dev->banks = banks; in fsl_ifc_ctrl_probe()
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| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | uncore-memory.json | 1019 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
1188 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
1198 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
1208 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
1218 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
1228 "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
1397 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
1407 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
1417 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
1427 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
[all …]
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | samsung,pinctrl-gpio-bank.yaml | 31 For GPIO banks supporting external GPIO interrupts or external wake-up
37 For GPIO banks supporting external GPIO interrupts or external wake-up
42 For GPIO banks supporting direct external wake-up interrupts (without
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| /linux/drivers/crypto/intel/qat/qat_common/ |
| H A D | adf_isr.c | 191 free_irq(irq, &etr_data->banks[i]); in adf_free_irqs()
212 /* Request msix irq for all banks unless SR-IOV enabled */ in adf_request_irqs()
215 struct adf_etr_bank_data *bank = &etr_data->banks[i]; in adf_request_irqs()
303 tasklet_init(&priv_data->banks[i].resp_handler, in adf_setup_bh()
305 (unsigned long)&priv_data->banks[i]); in adf_setup_bh()
316 tasklet_disable(&priv_data->banks[i].resp_handler); in adf_cleanup_bh()
317 tasklet_kill(&priv_data->banks[i].resp_handler); in adf_cleanup_bh()
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| /linux/drivers/clk/tegra/ |
| H A D | clk.c | 213 static int tegra_clk_periph_ctx_init(int banks) in tegra_clk_periph_ctx_init() argument
215 periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx), in tegra_clk_periph_ctx_init()
223 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) in tegra_clk_init() argument
227 if (WARN_ON(banks > ARRAY_SIZE(periph_regs))) in tegra_clk_init()
230 periph_clk_enb_refcnt = kcalloc(32 * banks, in tegra_clk_init()
236 periph_banks = banks; in tegra_clk_init()
247 if (tegra_clk_periph_ctx_init(banks)) { in tegra_clk_init()
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_crtc.h | 36 * @ATTACHED: all the context banks are attached.
37 * @DETACHED: all the context banks are detached.
38 * @ATTACH_ALL_REQ: transient state of attaching context banks.
39 * @DETACH_ALL_REQ: transient state of detaching context banks.
62 * @state: current state of smmu context banks
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | brcm,kona-gpio.yaml | 11 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
35 GPIO banks on the SoC. The interrupts must be ordered by bank, starting
36 with bank 0. There is always a 1:1 mapping between banks and IRQs.
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