Searched full:arria5 (Results 1 – 10 of 10) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | altera.yaml | 20 - altr,socfpga-arria5-socdk
21 - const: altr,socfpga-arria5
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | socfpga-dwmac.txt | 9 - compatible : For Cyclone5/Arria5 SoCs it should contain
16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
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| H A D | altr,socfpga-stmmac.yaml | 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
126 On Cyclone5/Arria5, the register shift represents the PHY mode
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| /freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/ |
| H A D | socfpga_arria5_socdk.dts | 10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | socfpga-reset.txt | 4 - compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
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| H A D | altr,rst-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /freebsd/sys/contrib/device-tree/Bindings/soc/altera/ |
| H A D | altr,sys-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /freebsd/sys/contrib/device-tree/Bindings/arm/altera/ |
| H A D | socfpga-clk-manager.yaml | 14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
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| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 6 Cyclone5 and Arria5 ECC Manager
55 and Arria5. Therefore the device tree is different as well.
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| H A D | altr,socfpga-ecc-manager.yaml | 15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
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