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/freebsd/sys/arm64/conf/
H A DALTERA2 # ALTERA -- Intel Altera kernel configuration file for FreeBSD/arm64
23 ident ALTERA
27 include "std.altera"
H A Dstd.altera2 # Altera SoC support
16 device dwc_socfpga # Altera SOCFPGA Ethernet MAC
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsocfpga-dw-mshc.txt1 * Altera SOCFPGA specific extensions to the Synopsys Designware Mobile
7 by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific
13 - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Daltera-passive-serial.txt1 Altera Passive Serial SPI FPGA Manager
3 Altera FPGAs support a method of loading the bitstream over what is
8 See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
H A Daltera-freeze-bridge.txt1 Altera Freeze Bridge Controller Driver
3 The Altera Freeze Bridge Controller manages one or more freeze bridges.
H A Daltera-pr-ip.txt1 Altera Arria10 Partial Reconfiguration IP
H A Daltera-fpga2sdram-bridge.txt1 Altera FPGA To SDRAM Bridge Driver
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-altera.txt1 * Altera I2C Controller
2 * This is Altera's synthesizable logic block I2C Controller for use
3 * in Altera's FPGAs.
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_vt.dts3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
10 model = "Altera SOCFPGA VT";
H A Dsocfpga_arria5_socdk.dts3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
9 model = "Altera SOCFPGA Arria V SoC Development Kit";
H A Dsocfpga_arria5.dtsi3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
H A Dsocfpga_arria10_socdk_sdmmc.dts3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
H A Dsocfpga_cyclone5_socdk.dts3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
9 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
H A Dsocfpga_cyclone5.dtsi3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
H A Dsocfpga_arria10_socdk.dtsi3 * Copyright (C) 2015 Altera Corporation <www.altera.com>
8 model = "Altera SOCFPGA Arria 10";
/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-sdram-controller.txt1 Altera SOCFPGA SDRAM Controller
5 syscon is required by the Altera SOCFPGA SDRAM EDAC.
H A Dsocfpga-clk-manager.yaml4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
7 title: Altera SOCFPGA Clock Manager
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Daltr,rst-mgr.yaml7 title: Altera SOCFPGA Reset Manager
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Daltr,msgdma.yaml7 title: Altera mSGDMA IP core
13 Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Daltera.yaml4 $id: http://devicetree.org/schemas/arm/altera.yaml#
7 title: Altera's SoCFPGA platform
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-altera.txt1 Altera GPIO controller bindings
17 hardware is synthesized. This field is required if the Altera GPIO controller
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Daltera_jtaguart.txt1 Altera JTAG UART
H A Daltera_uart.txt1 Altera UART
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi_altera.txt1 Altera SPI
/freebsd/sys/contrib/device-tree/Bindings/serio/
H A Daltera_ps2.txt1 Altera UP PS/2 controller

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