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/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
18 "xlnx,axi-fifo-mm-s-4.1"
19 "xlnx,axi-fifo-mm-s-4.2"
20 "xlnx,axi-fifo-mm-s-4.3"
25 - xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
26 - xlnx,axi-str-rxd-tdata-width: Should be <0x20>
27 - xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL"
28 - xlnx,axi-str-txc-tdata-width: Should be <0x20>
29 - xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
[all …]
H A DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
12 to the AXI Ethernet without the need to use DMA.
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-axi-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
7 title: Allwinner A10 AXI Clock
21 - allwinner,sun4i-a10-axi-clk
22 - allwinner,sun8i-a23-axi-clk
44 axi@1c20054 {
46 compatible = "allwinner,sun4i-a10-axi-clk";
49 clock-output-names = "axi";
55 compatible = "allwinner,sun8i-a23-axi-clk";
58 clock-output-names = "axi";
H A Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
30 clock is the AXI bus clock that needs to be enabled so we can access the
66 compatible = "adi,axi-clkgen-2.00.a";
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,axi-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
7 title: Analog Devices AXI ADC IP core
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
20 In some cases, the AXI ADC interface is used to perform specialized
26 - AXI AD7606x: specialized version of the IP core for all the chips from
37 - adi,axi-adc-10.0.a
38 - adi,axi-ad408x
39 - adi,axi-ad7606x
40 - adi,axi-ad485x
93 const: adi,axi-ad7606x
[all …]
H A Dxilinx-xadc.txt10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
33 when using the axi-xadc or the axi-system-management-wizard this must be
34 the clock that provides the clock to the AXI bus interface of the core.
110 compatible = "xlnx,axi-xadc-1.00.a";
/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
34 and length of the AXI DMA controller IO space, unless
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,glymur-rpmh.yaml154 - description: aggre PCIE_3A WEST AXI clock
155 - description: aggre PCIE_3B WEST AXI clock
156 - description: aggre PCIE_4 WEST AXI clock
157 - description: aggre PCIE_6 WEST AXI clock
169 - description: aggre PCIE_3B WEST AXI clock
170 - description: aggre PCIE_4 WEST AXI clock
171 - description: aggre PCIE_6 WEST AXI clock
183 - description: aggre PCIE_5 EAST AXI clock
195 - description: aggre USB3 TERT AXI clock
196 - description: aggre USB4_2 AXI clock
[all …]
H A Dqcom,sa8775p-rpmh.yaml58 - description: aggre UFS PHY AXI clock
59 - description: aggre QUP PRIM AXI clock
60 - description: aggre USB2 PRIM AXI clock
61 - description: aggre USB3 PRIM AXI clock
62 - description: aggre USB3 SEC AXI clock
74 - description: aggre UFS CARD AXI clock
H A Dqcom,sm8450-rpmh.yaml70 - description: aggre UFS PHY AXI clock
71 - description: aggre USB3 PRIM AXI clock
83 - description: aggre-NOC PCIe 0 AXI clock
84 - description: aggre-NOC PCIe 1 AXI clock
85 - description: aggre UFS PHY AXI clock
/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h3 * Definitions for Xilinx Axi Ethernet device driver.
74 /* Axi DMA Register definitions */
145 /* Axi Ethernet registers definition */
185 /* Bit Masks for Axi Ethernet RAF register */
204 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
209 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
229 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
233 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
237 /* Bit masks for Axi Ethernet RCW1 register */
253 /* Bit masks for Axi Ethernet TC register */
[all …]
H A Dxilinx_axienet_main.c3 * Xilinx Axi Ethernet device driver
13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
61 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
70 { .compatible = "xlnx,axi-ethernet-1.00.a", },
71 { .compatible = "xlnx,axi-ethernet-1.01.a", },
72 { .compatible = "xlnx,axi-ethernet-2.01.a", },
78 /* Option table for setting up Axi Ethernet hardware options */
144 * axienet_dma_in32 - Memory mapped Axi DMA register read
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dadi,axi-spdif-tx.txt1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
7 The controller expects two clocks, the clock used for the AXI interface and
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
24 compatible = "adi,axi-spdif-tx-1.00.a";
27 clock-names = "axi", "ref";
H A Dadi,axi-i2s.txt1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
28 compatible = "adi,axi-i2s-1.00.a";
31 clock-names = "axi", "ref";
/linux/Documentation/devicetree/bindings/pwm/
H A Dadi,axi-pwmgen.yaml4 $id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml#
7 title: Analog Devices AXI PWM generator
14 The Analog Devices AXI PWM generator can generate PWM signals
24 const: adi,axi-pwmgen-2.00.a
39 - const: axi
52 compatible = "adi,axi-pwmgen-2.00.a";
55 clock-names = "axi", "ext";
/linux/sound/soc/adi/
H A DMakefile2 snd-soc-adi-axi-i2s-y := axi-i2s.o
3 snd-soc-adi-axi-spdif-y := axi-spdif.o
5 obj-$(CONFIG_SND_SOC_ADI_AXI_I2S) += snd-soc-adi-axi-i2s.o
6 obj-$(CONFIG_SND_SOC_ADI_AXI_SPDIF) += snd-soc-adi-axi-spdif.o
H A DKconfig5 tristate "AXI-I2S support"
9 ASoC driver for the Analog Devices AXI-I2S softcore peripheral.
12 tristate "AXI-SPDIF support"
16 ASoC driver for the Analog Devices AXI-SPDIF softcore peripheral.
/linux/Documentation/devicetree/bindings/hwmon/
H A Dadi,axi-fan-control.yaml5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
8 title: Analog Devices AXI FAN Control
14 Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
22 - adi,axi-fan-control-1.00.a
51 fpga_axi: fpga-axi {
55 axi_fan_control: axi-fan-control@80000000 {
56 compatible = "adi,axi-fan-control-1.00.a";
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,pr-decoupler.yaml7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
21 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
23 eXchange AXI shutdown manager prevents AXI traffic from passing through the
26 preventing the system deadlock that can occur if AXI transactions are
38 - const: xlnx,dfx-axi-shutdown-manager-1.00
39 - const: xlnx,dfx-axi-shutdown-manager
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
124 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
130 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
131 * MB AXI Tunnel Master, which also has a mem map setup
133 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
134 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
148 /* MB AXI Target slaves */
155 /* MB AXI masters */
182 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
[all …]
/linux/Documentation/admin-guide/perf/
H A Dimx-ddr.rst17 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
49 This filter doesn't support filter different AXI ID for axid-read and axid-write
73 There is a limitation in previous AXI filter, it cannot filter different IDs
75 extension of AXI ID filter. One improvement is that counter 1-3 has their own
77 improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
82 --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
9 The cores on the AXI bus are automatically detected by bcma with the
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
/linux/Documentation/devicetree/bindings/usb/
H A Dstarfive,jh7110-usb.yaml42 - description: AXI clock
50 - const: axi
57 - description: AXI clock reset
64 - const: axi
97 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
102 reset-names = "pwrup", "apb", "axi", "utmi_apb";
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qp.dtsi33 clock-names = "axi";
42 clock-names = "axi";
51 clock-names = "axi";
60 clock-names = "axi";
69 clock-names = "ipg", "axi";
78 clock-names = "ipg", "axi";
/linux/Documentation/devicetree/bindings/w1/
H A Damd,axi-1wire-host.yaml4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
14 const: amd,axi-1wire-host
38 compatible = "amd,axi-1wire-host";

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