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/linux/Documentation/devicetree/bindings/cache/
H A Dandestech,ax45mp-cache.yaml5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
8 title: Andestech AX45MP L2 Cache Controller
23 - andestech,ax45mp-cache
31 - const: andestech,ax45mp-cache
73 compatible = "andestech,ax45mp-cache", "cache";
/linux/drivers/cache/
H A DKconfig5 bool "Andes Technology AX45MP L2 Cache controller"
9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
H A Dax45mp_cache.c3 * non-coherent cache functions for Andes AX45MP
175 { .compatible = "andestech,ax45mp-cache" },
194 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size in ax45mp_cache_init()
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
146 compatible = "andestech,ax45mp-cache", "cache";
/linux/arch/riscv/
H A DKconfig.errata4 bool "Andes AX45MP errata"
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml36 - andestech,ax45mp
H A Dextensions.yaml570 Registers in the AX45MP datasheet.
571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf