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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dandestech,ax45mp-cache.yaml5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
8 title: Andestech AX45MP L2 Cache Controller
23 - andestech,ax45mp-cache
32 - andestech,qilai-ax45mp-cache
33 - renesas,r9a07g043f-ax45mp-cache
34 - const: andestech,ax45mp-cache
76 const: andestech,qilai-ax45mp-cache
90 compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
/freebsd/sys/contrib/device-tree/src/riscv/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
45 compatible = "andestech,ax45mp", "riscv";
71 compatible = "andestech,ax45mp", "riscv";
97 compatible = "andestech,ax45mp", "riscv";
140 compatible = "andestech,qilai-ax45mp-cache",
141 "andestech,ax45mp-cache", "cache";
/freebsd/sys/contrib/device-tree/src/riscv/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
146 compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml49 - andestech,ax45mp
H A Dextensions.yaml662 Registers in the AX45MP datasheet.
663 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
/freebsd/sys/riscv/riscv/
H A Dplic.c255 * least the Renesas RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) in plic_map_intr()