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/linux/Documentation/arch/x86/
H A Dsva.rst17 PCIe Address Translation Services (ATS) along with Page Request Interface
20 specification Chapter 10: ATS Specification.
23 required to support the PCIe features ATS and PRI. ATS allows devices
26 sync. When an ATS lookup fails for a virtual address, the device should
28 CPU page tables. The device must use ATS again in order to fetch the
82 ATS. If the IOMMU responds with proper response that a page is not
259 use via Address Translation Service (ATS) requests. If the mapping exists
/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h272 * driver know where those addresses are by specifying the ATS field,
277 * Our hardware will refuse DDCB execution if the ATS field is not as
280 * will check that against the ATS field definition. Any invalid or
281 * unknown ATS content will lead to DDCB refusal.
356 #define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
371 * Address Translation Specification (ATS) definitions
373 * Each 4 bit within the ATS 64-bit word specify the required address
382 * The first 4 entries in the ATS word are reserved. The following nibbles
433 __u64 ats; member
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3-iommufd.c117 * as CD/ATS invalidations and vevents require a vSID to work properly. in arm_smmu_attach_prepare_vmaster()
176 * The VM has to control the actual ATS state at the PCI device because in arm_smmu_attach_dev_nested()
178 * think ATS is on it will not generate ATC flushes and the ATC will in arm_smmu_attach_dev_nested()
179 * become incoherent. Since we can't access the actual virtual PCI ATS in arm_smmu_attach_dev_nested()
232 * Only Full ATS or ATS UR is supported in arm_smmu_validate_vste()
/linux/drivers/misc/genwqe/
H A Dcard_ddcb.h39 #define ASIV_LENGTH 104 /* Old specification without ATS field */
40 #define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
H A Dcard_dev.c431 * When we receive a DDCB execution request with the ATS bits set to
589 } else { /* setup DDCB for ATS architecture */ in do_flash_update()
602 req->ats = 0x4ULL << 44; in do_flash_update()
711 } else { /* setup DDCB for ATS architecture */ in do_flash_read()
720 cmd->ats = 0x5ULL << 44; in do_flash_read()
878 ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs); in ddcb_cmd_fixups()
H A Dcard_ddcb.c849 * ATS field, which was introduced late. If the ATS field is in __genwqe_enqueue_ddcb()
851 * the ATS field is copied too, the code should do exactly in __genwqe_enqueue_ddcb()
852 * what it did before, but I wanted to make copying of the ATS in __genwqe_enqueue_ddcb()
860 pddcb->n.ats_64 = cpu_to_be64(req->cmd.ats); in __genwqe_enqueue_ddcb()
H A Dcard_base.h500 * according to the definitions required by the ATS field. It looks up
/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml111 ats-supported:
113 Indicates that a PCIe host controller supports ATS, and can handle Memory
/linux/Documentation/mm/
H A Dmmu_notifier.rst9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
31 Consider the following scenario (device use a feature similar to ATS/PASID):
/linux/include/net/nfc/
H A Dnfc.h90 * @ats: Answer To Select returned by an ISO 14443 Type A target upon activation
111 u8 ats[NFC_ATS_MAXSIZE]; member
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c1677 pi->rlp = eg_pi->ats[idx].rlp; in btc_set_at_for_uvd()
1678 pi->rmp = eg_pi->ats[idx].rmp; in btc_set_at_for_uvd()
1679 pi->lhp = eg_pi->ats[idx].lhp; in btc_set_at_for_uvd()
1680 pi->lmp = eg_pi->ats[idx].lmp; in btc_set_at_for_uvd()
2591 eg_pi->ats[0].rlp = RV770_RLP_DFLT; in btc_dpm_init()
2592 eg_pi->ats[0].rmp = RV770_RMP_DFLT; in btc_dpm_init()
2593 eg_pi->ats[0].lhp = RV770_LHP_DFLT; in btc_dpm_init()
2594 eg_pi->ats[0].lmp = RV770_LMP_DFLT; in btc_dpm_init()
2596 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; in btc_dpm_init()
2597 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; in btc_dpm_init()
[all …]
H A Dcypress_dpm.h88 struct at ats[2]; member
H A Dni_dpm.c4114 eg_pi->ats[0].rlp = RV770_RLP_DFLT; in ni_dpm_init()
4115 eg_pi->ats[0].rmp = RV770_RMP_DFLT; in ni_dpm_init()
4116 eg_pi->ats[0].lhp = RV770_LHP_DFLT; in ni_dpm_init()
4117 eg_pi->ats[0].lmp = RV770_LMP_DFLT; in ni_dpm_init()
4119 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; in ni_dpm_init()
4120 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; in ni_dpm_init()
4121 eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT; in ni_dpm_init()
4122 eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT; in ni_dpm_init()
/linux/sound/soc/codecs/
H A Dak4458.c523 int ats; in ak4458_set_dai_mute() local
528 ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT; in ak4458_set_dai_mute()
530 ndt = att_speed[ats] / (nfs / 1000); in ak4458_set_dai_mute()
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-pcduino3-nano.dts2 * Copyright 2015-2020 Adam Sampson <ats@offog.org>
/linux/net/nfc/nci/
H A Dntf.c696 pr_debug("ATS too long\n"); in nci_store_ats_nfc_iso_dep()
873 /* store ATS to be reported later in nci_activate_target */ in nci_rf_intf_activated_ntf_packet()
878 pr_err("unable to store ATS\n"); in nci_rf_intf_activated_ntf_packet()
/linux/drivers/iommu/intel/
H A Dnested.c16 #include <linux/pci-ats.h>
H A Dsvm.c14 #include <linux/pci-ats.h>
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dhwif.h80 void (*get_timestamp)(void *desc, u32 ats, u64 *ts);
82 int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts347 ats-supported;
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_irq.c89 "ATS",
/linux/drivers/iommu/iommufd/
H A Ddevice.c6 #include <linux/pci-ats.h>
1709 /* Report when ATS cannot be used for this device */ in iommufd_get_hw_info()
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Drule.c799 pr_warn("HWS: Invalid rule creation parameters (MTs, ATs or match params)\n"); in mlx5hws_rule_create()
/linux/include/linux/
H A Diommu.h275 /* ATS is supported and may be enabled for this device */
1146 /* ATS is supported */
/linux/drivers/accel/ivpu/
H A Divpu_hw_btrs.c551 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", in ivpu_hw_btrs_ats_print_lnl()

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