Home
last modified time | relevance | path

Searched full:ats (Results 1 – 25 of 62) sorted by relevance

123

/linux/drivers/pci/
H A Dats.c14 #include <linux/pci-ats.h>
35 * pci_ats_supported - check if the device can use ATS
38 * Returns true if the device supports ATS and is allowed to use it, false
51 * pci_prepare_ats - Setup the PS for ATS
56 * ensure that the VF can have ATS enabled.
84 * pci_enable_ats - enable the ATS capability
105 * Note that enabling ATS on a VF fails unless it's already enabled in pci_enable_ats()
125 * pci_disable_ats - disable the ATS capability
157 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
162 * The ATS spec uses 0 in the Invalidate Queue Depth field to
/linux/Documentation/arch/x86/
H A Dsva.rst17 PCIe Address Translation Services (ATS) along with Page Request Interface
20 specification Chapter 10: ATS Specification.
23 required to support the PCIe features ATS and PRI. ATS allows devices
26 sync. When an ATS lookup fails for a virtual address, the device should
28 CPU page tables. The device must use ATS again in order the fetch the
82 ATS. If the IOMMU responds with proper response that a page is not
259 use via Address Translation Service (ATS) requests. If the mapping exists
/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h272 * driver know where those addresses are by specifying the ATS field,
277 * Our hardware will refuse DDCB execution if the ATS field is not as
280 * will check that against the ATS field definition. Any invalid or
281 * unknown ATS content will lead to DDCB refusal.
356 #define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
371 * Address Translation Specification (ATS) definitions
373 * Each 4 bit within the ATS 64-bit word specify the required address
382 * The first 4 entries in the ATS word are reserved. The following nibbles
433 __u64 ats; member
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3-iommufd.c109 * The VM has to control the actual ATS state at the PCI device because in arm_smmu_attach_dev_nested()
111 * think ATS is on it will not generate ATC flushes and the ATC will in arm_smmu_attach_dev_nested()
112 * become incoherent. Since we can't access the actual virtual PCI ATS in arm_smmu_attach_dev_nested()
163 * Only Full ATS or ATS UR is supported in arm_smmu_validate_vste()
H A Darm-smmu-v3.c27 #include <linux/pci-ats.h>
1995 * ATS and PASID: in arm_smmu_atc_inv_to_cmd()
2023 * In an ATS Invalidate Request, the address must be aligned on the in arm_smmu_atc_inv_to_cmd()
2094 * ATS was enabled at the PCI device before completion of the TLBI. in arm_smmu_atc_inv_domain()
2590 dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); in arm_smmu_enable_ats()
2715 * If the device supports ATS then this determines if EATS should be enabled
2718 * The change of the EATS in the STE and the PCI ATS config space is managed by
2719 * this sequence to be in the right order so that if PCI ATS is enabled then
2722 * new_domain can be a non-paging domain. In this case ATS will not be enabled,
2743 * The SMMU does not support enabling ATS with bypass/abort. in arm_smmu_attach_prepare()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Denh_desc.c380 static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts) in enh_desc_get_timestamp() argument
384 if (ats) { in enh_desc_get_timestamp()
399 u32 ats) in enh_desc_get_rx_timestamp_status() argument
401 if (ats) { in enh_desc_get_rx_timestamp_status()
H A Dnorm_desc.c241 static void ndesc_get_timestamp(void *desc, u32 ats, u64 *ts) in ndesc_get_timestamp() argument
253 static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats) in ndesc_get_rx_timestamp_status() argument
H A Ddwxgmac2_descs.c87 static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts) in dwxgmac2_get_timestamp() argument
119 u32 ats) in dwxgmac2_get_rx_timestamp_status() argument
H A Ddwmac4_descs.c239 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts) in dwmac4_get_timestamp() argument
278 u32 ats) in dwmac4_wrback_get_rx_timestamp_status() argument
/linux/drivers/misc/genwqe/
H A Dcard_ddcb.h39 #define ASIV_LENGTH 104 /* Old specification without ATS field */
40 #define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
H A Dcard_dev.c431 * When we receive a DDCB execution request with the ATS bits set to
589 } else { /* setup DDCB for ATS architecture */ in do_flash_update()
602 req->ats = 0x4ULL << 44; in do_flash_update()
711 } else { /* setup DDCB for ATS architecture */ in do_flash_read()
720 cmd->ats = 0x5ULL << 44; in do_flash_read()
878 ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs); in ddcb_cmd_fixups()
H A Dcard_ddcb.c849 * ATS field, which was introduced late. If the ATS field is in __genwqe_enqueue_ddcb()
851 * the ATS field is copied too, the code should do exactly in __genwqe_enqueue_ddcb()
852 * what it did before, but I wanted to make copying of the ATS in __genwqe_enqueue_ddcb()
860 pddcb->n.ats_64 = cpu_to_be64(req->cmd.ats); in __genwqe_enqueue_ddcb()
/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml111 ats-supported:
113 Indicates that a PCIe host controller supports ATS, and can handle Memory
/linux/Documentation/admin-guide/perf/
H A Dnvidia-pmu.rst58 In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.
94 traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
229 | Destination | |GPU ATS |GPU Not-ATS| | Socket-B | Socket-B |
/linux/Documentation/mm/
H A Dmmu_notifier.rst9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
31 Consider the following scenario (device use a feature similar to ATS/PASID):
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gtt.c106 * FIXME: It is suspected that some Address Translation Service (ATS) in map_pt_dma()
110 * MTL until a proper ATS solution is found. in map_pt_dma()
130 * FIXME: It is suspected that some Address Translation Service (ATS) in map_pt_dma_locked()
134 * MTL until a proper ATS solution is found. in map_pt_dma_locked()
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu-v3.yaml16 and event queues and adding support for the ATS and PRI components of
/linux/include/net/nfc/
H A Dnfc.h90 * @ats: Answer To Select returned by an ISO 14443 Type A target upon activation
111 u8 ats[NFC_ATS_MAXSIZE]; member
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c1677 pi->rlp = eg_pi->ats[idx].rlp; in btc_set_at_for_uvd()
1678 pi->rmp = eg_pi->ats[idx].rmp; in btc_set_at_for_uvd()
1679 pi->lhp = eg_pi->ats[idx].lhp; in btc_set_at_for_uvd()
1680 pi->lmp = eg_pi->ats[idx].lmp; in btc_set_at_for_uvd()
2593 eg_pi->ats[0].rlp = RV770_RLP_DFLT; in btc_dpm_init()
2594 eg_pi->ats[0].rmp = RV770_RMP_DFLT; in btc_dpm_init()
2595 eg_pi->ats[0].lhp = RV770_LHP_DFLT; in btc_dpm_init()
2596 eg_pi->ats[0].lmp = RV770_LMP_DFLT; in btc_dpm_init()
2598 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; in btc_dpm_init()
2599 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; in btc_dpm_init()
[all …]
H A Dcypress_dpm.h88 struct at ats[2]; member
/linux/sound/soc/codecs/
H A Dak4458.c523 int ats; in ak4458_set_dai_mute() local
528 ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT; in ak4458_set_dai_mute()
530 ndt = att_speed[ats] / (nfs / 1000); in ak4458_set_dai_mute()
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-pcduino3-nano.dts2 * Copyright 2015-2020 Adam Sampson <ats@offog.org>
/linux/drivers/infiniband/hw/mlx5/
H A Dmr.c253 MLX5_SET(mkc, mkc, ma_translation_mode, !!ent->rb_key.ats); in set_cache_mkc()
632 res = key1.ats - key2.ats; in cache_ent_key_cmp()
714 smallest->rb_key.ats == rb_key.ats && in mkey_cache_ent_from_rb_key()
1047 MLX5_SET(mkc, mkc, ma_translation_mode, MLX5_CAP_GEN(dev->mdev, ats)); in mlx5_ib_get_dma_mr()
1129 rb_key.ats = mlx5_umem_needs_ats(dev, umem, access_flags); in alloc_cacheable_mr()
2162 MLX5_SET(mkc, mkc, ma_translation_mode, MLX5_CAP_GEN(dev->mdev, ats)); in mlx5_set_umr_free_mkey()
/linux/drivers/iommu/
H A Dof_iommu.c107 if (fwspec && of_property_read_bool(np, "ats-supported")) in of_pci_check_device_ats()
/linux/include/uapi/linux/
H A Diommufd.h572 * - ATS is a per-device property. If the VMM describes any devices as ATS
768 * The device TLB will be invalidated automatically if ATS is enabled.

123