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/linux/Documentation/arch/x86/
H A Dsva.rst17 PCIe Address Translation Services (ATS) along with Page Request Interface
20 specification Chapter 10: ATS Specification.
23 required to support the PCIe features ATS and PRI. ATS allows devices
26 sync. When an ATS lookup fails for a virtual address, the device should
28 CPU page tables. The device must use ATS again in order to fetch the
82 ATS. If the IOMMU responds with proper response that a page is not
259 use via Address Translation Service (ATS) requests. If the mapping exists
/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h272 * driver know where those addresses are by specifying the ATS field,
277 * Our hardware will refuse DDCB execution if the ATS field is not as
280 * will check that against the ATS field definition. Any invalid or
281 * unknown ATS content will lead to DDCB refusal.
356 #define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
371 * Address Translation Specification (ATS) definitions
373 * Each 4 bit within the ATS 64-bit word specify the required address
382 * The first 4 entries in the ATS word are reserved. The following nibbles
433 __u64 ats; member
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Denh_desc.c380 static void enh_desc_get_timestamp(void *desc, u32 ats, u64 *ts) in enh_desc_get_timestamp() argument
384 if (ats) { in enh_desc_get_timestamp()
399 u32 ats) in enh_desc_get_rx_timestamp_status() argument
401 if (ats) { in enh_desc_get_rx_timestamp_status()
H A Dnorm_desc.c241 static void ndesc_get_timestamp(void *desc, u32 ats, u64 *ts) in ndesc_get_timestamp() argument
253 static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats) in ndesc_get_rx_timestamp_status() argument
H A Dhwif.h85 void (*get_timestamp)(void *desc, u32 ats, u64 *ts);
87 int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
/linux/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c277 * ATS does not work on RK3588 when running in EP mode.
279 * After the host has enabled ATS on the EP side, it will send an IOTLB
282 * error, and the EP will not be operational. If we hide the ATS capability,
290 /* Only hide the ATS capability for RK3588 running in EP mode. */ in rockchip_pcie_ep_hide_broken_ats_cap_rk3588()
296 dev_err(dev, "failed to hide ATS capability\n"); in rockchip_pcie_ep_hide_broken_ats_cap_rk3588()
/linux/drivers/misc/genwqe/
H A Dcard_ddcb.h39 #define ASIV_LENGTH 104 /* Old specification without ATS field */
40 #define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
H A Dcard_dev.c431 * When we receive a DDCB execution request with the ATS bits set to
589 } else { /* setup DDCB for ATS architecture */ in do_flash_update()
602 req->ats = 0x4ULL << 44; in do_flash_update()
711 } else { /* setup DDCB for ATS architecture */ in do_flash_read()
720 cmd->ats = 0x5ULL << 44; in do_flash_read()
878 ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs); in ddcb_cmd_fixups()
H A Dcard_base.h500 * according to the definitions required by the ATS field. It looks up
/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml111 ats-supported:
113 Indicates that a PCIe host controller supports ATS, and can handle Memory
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c27 #include <linux/pci-ats.h>
2109 * ATS and PASID: in arm_smmu_atc_inv_to_cmd()
2137 * In an ATS Invalidate Request, the address must be aligned on the in arm_smmu_atc_inv_to_cmd()
2208 * ATS was enabled at the PCI device before completion of the TLBI. in arm_smmu_atc_inv_domain()
2671 dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); in arm_smmu_enable_ats()
2852 * If the device supports ATS then this determines if EATS should be enabled
2855 * The change of the EATS in the STE and the PCI ATS config space is managed by
2856 * this sequence to be in the right order so that if PCI ATS is enabled then
2859 * new_domain can be a non-paging domain. In this case ATS will not be enabled,
2881 * The SMMU does not support enabling ATS with bypass/abort. in arm_smmu_attach_prepare()
[all …]
/linux/Documentation/mm/
H A Dmmu_notifier.rst9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
31 Consider the following scenario (device use a feature similar to ATS/PASID):
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu-v3.yaml16 and event queues and adding support for the ATS and PRI components of
H A Driscv,iommu.yaml15 shared process address spaces including the ATS and PRI components of
/linux/include/net/nfc/
H A Dnfc.h90 * @ats: Answer To Select returned by an ISO 14443 Type A target upon activation
111 u8 ats[NFC_ATS_MAXSIZE]; member
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c1677 pi->rlp = eg_pi->ats[idx].rlp; in btc_set_at_for_uvd()
1678 pi->rmp = eg_pi->ats[idx].rmp; in btc_set_at_for_uvd()
1679 pi->lhp = eg_pi->ats[idx].lhp; in btc_set_at_for_uvd()
1680 pi->lmp = eg_pi->ats[idx].lmp; in btc_set_at_for_uvd()
2593 eg_pi->ats[0].rlp = RV770_RLP_DFLT; in btc_dpm_init()
2594 eg_pi->ats[0].rmp = RV770_RMP_DFLT; in btc_dpm_init()
2595 eg_pi->ats[0].lhp = RV770_LHP_DFLT; in btc_dpm_init()
2596 eg_pi->ats[0].lmp = RV770_LMP_DFLT; in btc_dpm_init()
2598 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; in btc_dpm_init()
2599 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; in btc_dpm_init()
[all …]
H A Dcypress_dpm.h88 struct at ats[2]; member
/linux/sound/soc/codecs/
H A Dak4458.c523 int ats; in ak4458_set_dai_mute() local
528 ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT; in ak4458_set_dai_mute()
530 ndt = att_speed[ats] / (nfs / 1000); in ak4458_set_dai_mute()
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-pcduino3-nano.dts2 * Copyright 2015-2020 Adam Sampson <ats@offog.org>
/linux/drivers/iommu/intel/
H A Dsvm.c14 #include <linux/pci-ats.h>
H A Dnested.c16 #include <linux/pci-ats.h>
/linux/drivers/iommu/
H A Dof_iommu.c105 if (fwspec && of_property_read_bool(np, "ats-supported")) in of_pci_check_device_ats()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.h679 struct at ats[2]; member
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts347 ats-supported;
/linux/include/uapi/linux/
H A Dpci_regs.h934 #define PCI_ATS_CAP 0x04 /* ATS Capability Register */
938 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */
939 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */

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