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/linux/Documentation/arch/x86/
H A Dsva.rst17 PCIe Address Translation Services (ATS) along with Page Request Interface
20 specification Chapter 10: ATS Specification.
23 required to support the PCIe features ATS and PRI. ATS allows devices
26 sync. When an ATS lookup fails for a virtual address, the device should
28 CPU page tables. The device must use ATS again in order to fetch the
82 ATS. If the IOMMU responds with proper response that a page is not
259 use via Address Translation Service (ATS) requests. If the mapping exists
/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h272 * driver know where those addresses are by specifying the ATS field,
277 * Our hardware will refuse DDCB execution if the ATS field is not as
280 * will check that against the ATS field definition. Any invalid or
281 * unknown ATS content will lead to DDCB refusal.
356 #define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */
371 * Address Translation Specification (ATS) definitions
373 * Each 4 bit within the ATS 64-bit word specify the required address
382 * The first 4 entries in the ATS word are reserved. The following nibbles
433 __u64 ats; member
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3-iommufd.c114 * as CD/ATS invalidations and vevents require a vSID to work properly. in arm_smmu_attach_prepare_vmaster()
173 * The VM has to control the actual ATS state at the PCI device because in arm_smmu_attach_dev_nested()
175 * think ATS is on it will not generate ATC flushes and the ATC will in arm_smmu_attach_dev_nested()
176 * become incoherent. Since we can't access the actual virtual PCI ATS in arm_smmu_attach_dev_nested()
229 * Only Full ATS or ATS UR is supported in arm_smmu_validate_vste()
H A Darm-smmu-v3.c27 #include <linux/pci-ats.h>
1245 /* The lock is required to fence concurrent ATS operations. */ in arm_smmu_write_entry()
1360 * logic already will have the PCI cap for ATS disabled. Thus at this in arm_smmu_alloc_cd_ptr()
1361 * moment we can expect that the device will not generate ATS queries in arm_smmu_alloc_cd_ptr()
1364 * that issue ATS when the PCI config space is disabled. However, if in arm_smmu_alloc_cd_ptr()
2429 * ATS and PASID: in arm_smmu_tlb_inv_range_domain()
2457 * In an ATS Invalidate Request, the address must be aligned on the in arm_smmu_tlb_inv_page_nosync()
2641 /* ATS must be after a sync of the S1/S2 invalidations */ in arm_smmu_domain_finalise()
2762 * Avoid locking unless ATS is being used. No ATC invalidation can be in arm_smmu_enable_pasid()
3069 dev_err(master->dev, "Failed to enable ATS (ST in arm_smmu_attach_dev()
[all...]
/linux/drivers/misc/genwqe/
H A Dcard_ddcb.h39 #define ASIV_LENGTH 104 /* Old specification without ATS field */
40 #define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
H A Dcard_dev.c431 * When we receive a DDCB execution request with the ATS bits set to
589 } else { /* setup DDCB for ATS architecture */ in do_flash_update()
602 req->ats = 0x4ULL << 44; in do_flash_update()
711 } else { /* setup DDCB for ATS architecture */ in do_flash_read()
720 cmd->ats = 0x5ULL << 44; in do_flash_read()
878 ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs); in ddcb_cmd_fixups()
H A Dcard_ddcb.c849 * ATS field, which was introduced late. If the ATS field is in __genwqe_enqueue_ddcb()
851 * the ATS field is copied too, the code should do exactly in __genwqe_enqueue_ddcb()
852 * what it did before, but I wanted to make copying of the ATS in __genwqe_enqueue_ddcb()
860 pddcb->n.ats_64 = cpu_to_be64(req->cmd.ats); in __genwqe_enqueue_ddcb()
/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml111 ats-supported:
113 Indicates that a PCIe host controller supports ATS, and can handle Memory
/linux/Documentation/mm/
H A Dmmu_notifier.rst9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
31 Consider the following scenario (device use a feature similar to ATS/PASID):
/linux/include/net/nfc/
H A Dnfc.h90 * @ats: Answer To Select returned by an ISO 14443 Type A target upon activation
111 u8 ats[NFC_ATS_MAXSIZE]; member
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c1677 pi->rlp = eg_pi->ats[idx].rlp; in btc_set_at_for_uvd()
1678 pi->rmp = eg_pi->ats[idx].rmp; in btc_set_at_for_uvd()
1679 pi->lhp = eg_pi->ats[idx].lhp; in btc_set_at_for_uvd()
1680 pi->lmp = eg_pi->ats[idx].lmp; in btc_set_at_for_uvd()
2591 eg_pi->ats[0].rlp = RV770_RLP_DFLT; in btc_dpm_init()
2592 eg_pi->ats[0].rmp = RV770_RMP_DFLT; in btc_dpm_init()
2593 eg_pi->ats[0].lhp = RV770_LHP_DFLT; in btc_dpm_init()
2594 eg_pi->ats[0].lmp = RV770_LMP_DFLT; in btc_dpm_init()
2596 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; in btc_dpm_init()
2597 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; in btc_dpm_init()
[all …]
H A Dcypress_dpm.h88 struct at ats[2]; member
H A Dni_dpm.c4114 eg_pi->ats[0].rlp = RV770_RLP_DFLT; in ni_dpm_init()
4115 eg_pi->ats[0].rmp = RV770_RMP_DFLT; in ni_dpm_init()
4116 eg_pi->ats[0].lhp = RV770_LHP_DFLT; in ni_dpm_init()
4117 eg_pi->ats[0].lmp = RV770_LMP_DFLT; in ni_dpm_init()
4119 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT; in ni_dpm_init()
4120 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT; in ni_dpm_init()
4121 eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT; in ni_dpm_init()
4122 eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT; in ni_dpm_init()
/linux/sound/soc/codecs/
H A Dak4458.c523 int ats; in ak4458_set_dai_mute() local
528 ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT; in ak4458_set_dai_mute()
530 ndt = att_speed[ats] / (nfs / 1000); in ak4458_set_dai_mute()
/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml15 shared process address spaces including the ATS and PRI components of
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-pcduino3-nano.dts2 * Copyright 2015-2020 Adam Sampson <ats@offog.org>
/linux/net/nfc/nci/
H A Dntf.c674 pr_debug("ATS too long\n"); in nci_store_ats_nfc_iso_dep()
849 /* store ATS to be reported later in nci_activate_target */ in nci_rf_intf_activated_ntf_packet()
854 pr_err("unable to store ATS\n"); in nci_rf_intf_activated_ntf_packet()
/linux/drivers/iommu/intel/
H A Diommu.c21 #include <linux/pci-ats.h>
187 u8 atc_required:1; /* ATS is required */
2239 * This device supports ATS as it is in SATC table. in dmar_ats_supported()
2240 * When IOMMU is in legacy mode, enabling ATS is done in dmar_ats_supported()
2242 * ATS, hence OS should not enable this device ATS in dmar_ats_supported()
2249 /* If it's an integrated device, allow ATS */ in dmar_ats_supported()
2252 /* Connected via non-PCIe: no ATS */ in dmar_ats_supported()
3331 * device is undefined if you enable PASID support after ATS support. in intel_iommu_probe_finalize()
4123 * Here we deal with a device TLB defect where device may inadvertently issue ATS
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H A Dnested.c16 #include <linux/pci-ats.h>
H A Dsvm.c14 #include <linux/pci-ats.h>
H A Dpasid.c18 #include <linux/pci-ats.h>
931 * Intel IOMMU from waiting indefinitely for an ATS invalidation that in __context_flush_dev_iotlb()
/linux/drivers/infiniband/hw/mlx5/
H A Dmr.c253 MLX5_SET(mkc, mkc, ma_translation_mode, !!ent->rb_key.ats); in set_cache_mkc()
639 res = key1.ats - key2.ats; in cache_ent_key_cmp()
729 smallest->rb_key.ats == rb_key.ats && in mkey_cache_ent_from_rb_key()
1076 MLX5_SET(mkc, mkc, ma_translation_mode, MLX5_CAP_GEN(dev->mdev, ats)); in mlx5_ib_get_dma_mr()
1160 rb_key.ats = mlx5_umem_needs_ats(dev, umem, access_flags); in alloc_cacheable_mr()
2298 MLX5_SET(mkc, mkc, ma_translation_mode, MLX5_CAP_GEN(dev->mdev, ats)); in mlx5_set_umr_free_mkey()
/linux/include/uapi/linux/
H A Diommufd.h458 * allocated nested domain, as CD/ATS invalidations and vevents need a vSID.
598 * - ATS is a per-device property. If the VMM describes any devices as ATS
698 * @IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED: ATS is not supported or cannot be used
699 * on this device (absence implies ATS
883 * The device TLB will be invalidated automatically if ATS is enabled.
/linux/drivers/iommu/
H A Dof_iommu.c105 if (fwspec && of_property_read_bool(np, "ats-supported")) in of_pci_check_device_ats()
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts347 ats-supported;

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