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/linux/drivers/clk/bcm/
H A Dclk-iproc-asiu.c20 struct iproc_asiu *asiu; member
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable() local
42 /* some clocks at the ASIU level are always enabled */ in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
56 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_disable() local
59 /* some clocks at the ASIU level are always enabled */ in iproc_asiu_clk_disable()
63 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
65 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
72 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_recalc_rate() local
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H A Dclk-iproc.h22 /* PLL that requires gating through ASIU */
98 * Clock gating control at the top ASIU level
158 struct iproc_asiu_gate asiu; member
191 * Divisor of the ASIU clocks
H A Dclk-iproc-pll.c181 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_disable()
182 val &= ~(1 << ctrl->asiu.en_shift); in __pll_disable()
183 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_disable()
223 /* certain PLLs also need to be ungated from the ASIU top level */ in __pll_enable()
225 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_enable()
226 val |= (1 << ctrl->asiu.en_shift); in __pll_enable()
227 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_enable()
754 /* some PLLs require gating control at the top ASIU level */ in iproc_pll_clk_setup()
H A DMakefile9 obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
H A Dclk-cygnus.c187 .asiu = ASIU_GATE_VAL(0x0, 3),
260 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,iproc-clocks.yaml19 ASIU clocks are a special case. These clocks are derived directly from the
30 - brcm,cygnus-asiu-clk
56 - description: ASIU or split status register
59 description: The input parent clock phandle for the PLL / ASIU clock. For
97 - brcm,cygnus-asiu-clk
113 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
114 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
115 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
406 compatible = "brcm,cygnus-asiu-clk";
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,iproc-gpio.txt13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
97 compatible = "brcm,cygnus-asiu-gpio";
118 /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */
/linux/drivers/pinctrl/bcm/
H A DKconfig122 The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
123 GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
H A Dpinctrl-iproc-gpio.c8 * GPIO controllers on Iproc including the ASIU GPIO controller, the
49 /* drive strength control for ASIU GPIO */
795 { .compatible = "brcm,cygnus-asiu-gpio" },
H A Dpinctrl-cygnus-mux.c10 * function, and therefore be controlled by the Cygnus ASIU GPIO controller
/linux/include/dt-bindings/clock/
H A Dbcm-cygnus.h63 /* ASIU clock ID */
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus-clock.dtsi118 compatible = "brcm,cygnus-asiu-clk";
H A Dbcm-cygnus.dtsi516 compatible = "brcm,cygnus-asiu-gpio";