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/linux/arch/arm/kernel/
H A Dfiqasm.S29 mov r0, r0 @ avoid hazard prior to ARMv4
34 mov r0, r0 @ avoid hazard prior to ARMv4
42 mov r0, r0 @ avoid hazard prior to ARMv4
47 mov r0, r0 @ avoid hazard prior to ARMv4
/linux/arch/arm/include/asm/
H A Dglue-df.h19 * v4_early - ARMv4 without Thumb early abort handler
20 * v4t_late - ARMv4 with Thumb late abort handler
21 * v4t_early - ARMv4 with Thumb early abort handler
H A Dtlbflush.h54 * v4 - ARMv4 without write buffer
55 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
56 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
H A Delf.h95 * ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
/linux/arch/arm/mm/
H A Dcopypage-v4wb.c11 * ARMv4 optimised copy_user_highpage
18 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
61 * ARMv4 optimised clear_user_page
H A Dcopypage-v4mc.c29 * ARMv4 mini-dcache optimised copy_user_highpage
36 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
85 * ARMv4 optimised clear_user_page
H A Dcopypage-v4wt.c14 * ARMv4 optimised copy_user_highpage
56 * ARMv4 optimised clear_user_page
H A Dfsr-2level.c4 * The following are the standard ARMv3 and ARMv4 aborts. ARMv5
H A Dproc-arm740.S137 string cpu_arch_name, "armv4"
H A Dcache-v4wt.S7 * ARMv4 write through cache operations support.
H A Dproc-fa526.S188 string cpu_arch_name, "armv4"
H A Dproc-sa110.S200 string cpu_arch_name, "armv4"
H A DKconfig165 The FA526 is a version of the ARMv4 compatible processor with
905 run on ARMv4 through to ARMv7 without modification.
H A Dproc-sa1100.S242 string cpu_arch_name, "armv4"
/linux/arch/arm/lib/
H A DMakefile36 lib-y += io-readsw-armv4.o io-writesw-armv4.o
H A Ddelay-loop.S13 .arch armv4
H A Dio-writesw-armv4.S3 * linux/arch/arm/lib/io-writesw-armv4.S
H A Dio-readsw-armv4.S3 * linux/arch/arm/lib/io-readsw-armv4.S
/linux/lib/crypto/
H A DMakefile133 $(obj)/arm/poly1305-core.S: $(src)/arm/poly1305-armv4.pl
196 libsha1-y += arm/sha1-armv4-large.o
220 $(obj)/arm/sha256-core.S: $(src)/arm/sha256-armv4.pl
250 $(obj)/arm/sha512-core.S: $(src)/arm/sha512-armv4.pl
/linux/lib/crypto/arm/
H A Dsha1-armv4-large.S19 @ sha1_block procedure for ARMv4.
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
506 .asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
H A Dsha512-armv4.pl19 # SHA512 block procedure for ARMv4. September 2007.
637 .asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
645 $code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
H A Dsha256-armv4.pl19 # SHA256 block procedure for ARMv4. May 2007.
675 .asciz "SHA256 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
719 s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
/linux/arch/arm/boot/compressed/
H A Dhead-sa1100.S15 .arch armv4
/linux/Documentation/devicetree/bindings/arm/
H A Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
H A Dgemini.yaml10 The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally

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