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/freebsd/sys/conf/
H A Dfiles.arm2 arm/arm/autoconf.c standard
3 arm/arm/bcopy_page.S standard
4 arm/arm/bcopyinout.S standard
5 arm/arm/blockio.S standard
6 arm/arm/bus_space_asm_generic.S standard
7 arm/arm/bus_space_base.c optional fdt
8 arm/arm/bus_space_generic.c standard
9 arm/arm/busdma_machdep.c standard
10 arm/arm/copystr.S standard
11 arm/arm/cpufunc.c standard
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
74 ARM::AEK_NONE)
76 ARM::AEK_NONE)
78 ARM::AEK_NONE)
80 ARM::AEK_NONE)
82 FK_NONE, ARM::AEK_DSP)
84 FK_NONE, ARM::AEK_DSP)
86 ARM::AEK_DSP)
88 ARM::AEK_DSP)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp16 #include "ARM.h"
32 #define DEBUG_TYPE "arm-pseudo"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
36 cl::desc("Verify machine code after expanding ARM pseudos"));
38 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
170 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
171 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
172 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
173 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
174 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
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H A DARMFeatures.h1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
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H A DARMRegisterBankInfo.cpp9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
30 namespace ARM { namespace
130 } // end namespace arm
137 // (ARM::RegBanks) is unique in the compiler. At some point, it in ARMRegisterBankInfo()
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
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H A DThumb2InstrInfo.cpp53 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
92 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
180 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
181 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
196 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
199 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
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H A DARMBaseInstrInfo.cpp1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
73 #define DEBUG_TYPE "arm-instrinfo"
90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
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H A DARMInstrInfo.cpp1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
9 // This file contains the ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
34 NopInst.setOpcode(ARM::HINT); in getNop()
39 NopInst.setOpcode(ARM::MOVr); in getNop()
40 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
41 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
53 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
54 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
55 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
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H A DARMBaseInstrInfo.h1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
116 /// enhance debug entry value descriptions for ARM targets.
352 /// ARM supports the MachineOutliner.
378 return MI->getOpcode() == ARM::t2LoopEndDec || in isUnspillableTerminatorImpl()
379 MI->getOpcode() == ARM::t2DoLoopStartTP || in isUnspillableTerminatorImpl()
380 MI->getOpcode() == ARM::t2WhileLoopStartLR || in isUnspillableTerminatorImpl()
381 MI->getOpcode() == ARM::t2WhileLoopStartTP; in isUnspillableTerminatorImpl()
556 return MachineOperand::CreateReg(ARM::CPSR,
563 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
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H A DARMFixCortexA57AES1742098Pass.cpp35 #include "ARM.h"
63 #define DEBUG_TYPE "arm-fix-cortex-a57-aes-1742098"
80 return "ARM fix for Cortex-A57 AES Erratum 1742098"; in getPassName()
113 "ARM fix for Cortex-A57 AES Erratum 1742098", false,
117 "ARM fix for Cortex-A57 AES Erratum 1742098", false, false)
123 return Opc == ARM::AESD || Opc == ARM::AESE; in isFirstAESPairInstr()
139 case ARM::AESD: in isSafeAESInput()
140 case ARM::AESE: in isSafeAESInput()
141 case ARM::AESMC: in isSafeAESInput()
142 case ARM::AESIMC: in isSafeAESInput()
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H A DARMLoadStoreOptimizer.cpp1 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
14 #include "ARM.h"
72 #define DEBUG_TYPE "arm-ldst-opt"
92 AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
93 cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
95 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
201 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
208 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
219 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
223 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMELFObjectWriter.cpp1 //===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===//
90 case ARM::S_GOTTPOFF: in getRelocType()
91 case ARM::S_GOTTPOFF_FDPIC: in getRelocType()
92 case ARM::S_TLSCALL: in getRelocType()
93 case ARM::S_TLSDESC: in getRelocType()
94 case ARM::S_TLSGD: in getRelocType()
95 case ARM::S_TLSGD_FDPIC: in getRelocType()
96 case ARM::S_TLSLDM: in getRelocType()
97 case ARM::S_TLSLDM_FDPIC: in getRelocType()
98 case ARM::S_TLSLDO: in getRelocType()
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H A DARMTargetStreamer.cpp111 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} in emitArch()
113 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} in emitObjectArch()
114 void ARMTargetStreamer::emitFPU(ARM::FPUKind FPU) {} in emitFPU()
139 if (STI.hasFeature(ARM::HasV9_0aOps)) in getArchForCPU()
141 else if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
142 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
145 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
147 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
149 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
150 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dpmu.yaml4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
7 title: ARM Performance Monitor Units
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
27 - arm,armv8-pmuv3 # Only for s/w models
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
30 - arm,arm11mpcore-pmu
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H A Dcpus.yaml4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
7 title: ARM CPUs
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
37 The ARM architecture, in accordance with the Devicetree Specification,
45 Usage and definition depend on ARM architecture version and configuration:
47 On uniprocessor ARM architectures previous to v7 this property is required
50 On ARM 11 MPcore based systems this property is required and matches the
57 On 32-bit ARM v7 or later systems this property is required and matches
64 On ARM v8 64-bit systems this property is required and matches the
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H A Darm,vexpress-juno.yaml4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
7 title: ARM Versatile Express and Juno Boards
10 - Sudeep Holla <sudeep.holla@arm.com>
14 ARM's Versatile Express platform were built as reference designs for exploring
30 "arm,vexpress" compatible was retained in the root node, and these are
36 manual, followed by "arm,vexpress" as an additional compatible value. If
46 in MPCore configuration in a test chip on the core tile. See ARM
49 - const: arm,vexpress,v2p-ca9
50 - const: arm,vexpres
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H A Darm,coresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
31 are implementation defined, except when the CTI is connected to an ARM v8
34 In this case the ARM v8 architecture defines the required signal connections
37 indicate this feature (arm,coresight-cti-v8-arch).
52 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
66 - $ref: /schemas/arm/primecell.yaml#
68 # Need a custom select here or 'arm,primecell' will match on lots of nodes
74 - arm,coresigh
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H A Dcoresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
32 are implementation defined, except when the CTI is connected to an ARM v8
35 In this case the ARM v8 architecture defines the required signal connections
38 indicate this feature (arm,coresight-cti-v8-arch).
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
67 - $ref: /schemas/arm/primecell.yaml#
69 # Need a custom select here or 'arm,primecell' will match on lots of nodes
75 - arm,coresight-cti
85 - const: arm,coresight-cti
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H A Dvexpress-config.yaml4 $id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
7 title: ARM Versatile Express configuration bus
10 - Andre Przywara <andre.przywara@arm.com>
20 const: arm,vexpress,config-bus
22 arm,vexpress,config-bridge:
31 const: arm,vexpress-muxfpga
33 arm,vexpress-sysreg,func:
43 - arm,vexpress-sysreg,func
49 const: arm,vexpress-shutdown
51 arm,vexpress-sysreg,func:
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/freebsd/sys/arm/nvidia/tegra124/
H A Dfiles.tegra1245 arm/nvidia/tegra124/tegra124_machdep.c standard
6 arm/nvidia/tegra124/tegra124_mp.c optional smp
7 arm/nvidia/tegra124/tegra124_car.c standard
8 arm/nvidia/tegra124/tegra124_clk_pll.c standard
9 arm/nvidia/tegra124/tegra124_clk_per.c standard
10 arm/nvidia/tegra124/tegra124_clk_super.c standard
11 arm/nvidia/tegra124/tegra124_xusbpadctl.c standard
12 arm/nvidia/tegra124/tegra124_pmc.c standard
13 arm/nvidia/tegra124/tegra124_cpufreq.c standard
14 arm/nvidia/tegra124/tegra124_coretemp.c standard
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
9 // This file implements a target parser to recognise ARM hardware features
26 .Case("thumb,arm", "arm,thumb") in getHWDivSynonym()
31 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
42 unsigned ARM::parseArchVersion(StringRef Arch) { in parseArchVersion()
98 static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) { in getProfileKind()
100 case ARM::ArchKind::ARMV6M: in getProfileKind()
101 case ARM::ArchKind::ARMV7M: in getProfileKind()
102 case ARM::ArchKind::ARMV7EM: in getProfileKind()
103 case ARM::ArchKind::ARMV8MMainline: in getProfileKind()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
35 #define DEBUG_TYPE "arm-disassembler"
130 /// ARM disassembler for all ARM platforms.
138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) in ARMDisassembler()
721 case ARM::HVC: { in checkDecodedInstruction()
731 case ARM::t2ADDri: in checkDecodedInstruction()
732 case ARM::t2ADDri12: in checkDecodedInstruction()
733 case ARM::t2ADDrr: in checkDecodedInstruction()
734 case ARM::t2ADDrs: in checkDecodedInstruction()
735 case ARM::t2SUBri: in checkDecodedInstruction()
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-base.dtsi11 compatible = "arm,armv7-timer-mem";
25 compatible = "arm,mhu", "arm,primecell";
36 compatible = "arm,mmu-400", "arm,smmu-v1";
48 compatible = "arm,mmu-401", "arm,smmu-v1";
59 compatible = "arm,mmu-401", "arm,smmu-v1";
70 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 compatible = "arm,gic-v2m-frame";
89 compatible = "arm,gic-v2m-frame";
95 compatible = "arm,gic-v2m-frame";
101 compatible = "arm,gic-v2m-frame";
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/freebsd/sys/contrib/device-tree/src/arm64/lg/
H A Dlg131x.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 compatible = "arm,cortex-a53";
29 compatible = "arm,cortex-a53";
36 compatible = "arm,cortex-a53";
43 compatible = "arm,cortex-a53";
56 compatible = "arm,psci-0.2", "arm,psci";
65 compatible = "arm,gic-400";
74 compatible = "arm,cortex-a53-pmu";
86 compatible = "arm,armv8-timer";
114 compatible = "arm,sp804", "arm,primecell";
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/freebsd/sys/arm/ti/
H A Dfiles.ti2 arm/ti/ti_cpuid.c standard
3 arm/ti/ti_machdep.c standard
4 arm/ti/ti_prcm.c standard
5 arm/ti/ti_omap4_cm.c standard
6 arm/ti/ti_scm.c standard
7 arm/ti/ti_scm_syscon.c standard
8 arm/ti/ti_pinmux.c standard
10 arm/ti/ti_mbox.c optional ti_mbox
11 arm/ti/ti_pruss.c optional ti_pruss
12 arm/ti/ti_prm.c optional ti_pruss
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