Home
last modified time | relevance | path

Searched +full:arc +full:- +full:hs (Results 1 – 20 of 20) sorted by relevance

/linux/Documentation/arch/arc/
H A Darc.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Linux kernel for ARC processors
10 ARC processors and relevant open source projects.
12 - `<https://embarc.org>`_ - Community portal for open source on ARC.
16 - `<https://github.com/foss-for-synopsys-dwc-arc-processors>`_ -
18 ARC processors. Some of the projects are forks of various upstream projects,
21 as open source for use on ARC Processors.
23 - `Official Synopsys ARC Processors website
24 <https://www.synopsys.com/designware-ip/processor-solutions.html>`_ -
26 Manual, AKA PRM for ARC HS processors
[all …]
/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 config ARC config
86 menu "ARC Architecture Configuration"
88 menu "ARC Platform/SoC/Board"
90 source "arch/arc/plat-tb10x/Kconfig"
91 source "arch/arc/plat-axs10x/Kconfig"
92 source "arch/arc/plat-hsdk/Kconfig"
97 prompt "ARC Instruction Set"
104 The original ARC ISA of ARC600/700 cores
[all …]
/linux/Documentation/devicetree/bindings/arc/
H A Dsnps,archs-pct.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC HS Performance Counters
10 - Aryabhatta Dey <aryabhattadey35@gmail.com>
13 The ARC HS can be configured with a pipeline performance monitor for counting
20 const: snps,archs-pct
29 - compatible
30 - reg
[all …]
H A Dhsdk.txt1 Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
2 ---------------------------------------------------------------------------
4 ARC HSDK Board with quad-core ARC HS38x4 in silicon.
7 - compatible = "snps,hsdk";
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,archs-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/snps,archs-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS incore Interrupt Controller
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS incore Interrupt Controller provided by cores implementing ARCv2 ISA.
14 intc accessed via the special ARC AUX register interface, hence "reg" property
19 const: snps,archs-intc
21 interrupt-controller: true
[all …]
H A Dsnps,archs-idu-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS Interrupt Distribution Unit
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt
17 The interrupt controller is accessed via the special ARC AUX register
22 const: snps,archs-idu-intc
24 interrupt-controller: true
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dsnps,arc-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,arc-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys ARC Local Timer
10 - Vineet Gupta <vgupta@synopsys.com>
13 Synopsys ARC Local Timer with Interrupt Capabilities
15 - Found on all ARC CPUs (ARC700/ARCHS)
16 - Can be optionally programmed to interrupt on Limit
17 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
[all …]
H A Dsnps,archs-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
10 - Vineet Gupta <vgupta@synopsys.com>
14 const: snps,archs-rtc
20 - compatible
21 - clocks
26 - |
[all …]
H A Dsnps,archs-gfrc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-gfrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
10 - Vineet Gupta <vgupta@synopsys.com>
14 const: snps,archs-gfrc
20 - compatible
21 - clocks
26 - |
[all …]
/linux/arch/arc/plat-hsdk/
H A Dplatform.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARC HSDK Platform support code
36 * --------------------- in hsdk_enable_gpio_intc_wire()
37 * | snps,archs-intc | in hsdk_enable_gpio_intc_wire()
38 * --------------------- in hsdk_enable_gpio_intc_wire()
40 * ---------------------- in hsdk_enable_gpio_intc_wire()
41 * | snps,archs-idu-intc | in hsdk_enable_gpio_intc_wire()
42 * ---------------------- in hsdk_enable_gpio_intc_wire()
46 * ------------------- in hsdk_enable_gpio_intc_wire()
47 * | snps,dw-apb-intc | in hsdk_enable_gpio_intc_wire()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "ARC HS Development Kit SOC"
/linux/arch/arc/kernel/
H A Dmcip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
12 #include <soc/arc/mcip.h>
13 #include <asm/irqflags-arcv2.h>
24 * Only works for ARC HS v3.0+, on earlier versions has no effect.
71 * STATUS32[H]/actionpoint/breakpoint/self-halt in mcip_update_debug_halt_mask()
114 * see arch/arc/kernel/smp.c: ipi_send_msg_one() in mcip_ipi_send()
184 * -dynamic routing (IRQ affinity)
185 * -load balancing (Round Robin interrupt distribution)
186 * -1:N distribution
[all …]
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
31 #include <asm/dsp-impl.h>
32 #include <soc/arc/mcip.h>
38 /* Part of U-boot ABI: see head.S */
100 if (info->arcver < 0x34) in arcompact_mumbojumbo()
105 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s (%s ISA) %s%s%s\n", in arcompact_mumbojumbo()
108 IS_AVAIL1(be, "[Big-Endian]")); in arcompact_mumbojumbo()
114 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", in arcompact_mumbojumbo()
120 bpu_cache = 256 << (bpu.ent - 1); in arcompact_mumbojumbo()
[all …]
/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * Device Tree for ARC HS Development Kit
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
/linux/arch/arc/mm/
H A Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a separate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
14 * entry, so that it doesn't knock out its I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARC Cache Management
5 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
55 p_slc->sz_k = 128 << slc_cfg.sz; in read_decode_cache_bcr_arcv2()
56 l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; in read_decode_cache_bcr_arcv2()
57 n += scnprintf(buf + n, len - n, in read_decode_cache_bcr_arcv2()
59 p_slc->sz_k, p_slc->line_len, IS_USED_RUN(slc_enable)); in read_decode_cache_bcr_arcv2()
84 /* HS 2.0 didn't have AUX_VOL */ in read_decode_cache_bcr_arcv2()
88 /* HS 3.0 has limit and strict-ordering fields */ in read_decode_cache_bcr_arcv2()
[all …]
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
191 * causing h/w - s/w ASID to get out of sync) in local_flush_tlb_mm()
[all …]
/linux/tools/perf/util/
H A Ddisasm.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <subcmd/run-command.h>
15 #include "annotate-data.h"
16 #include "build-id.h"
21 #include "dwarf-regs.h"
35 /* These can be referred from the arch-dependent code */
57 regcomp(&file_lineno, "^/[^:]+:([0-9]+)", REG_EXTENDED); in symbol__init_regexpr()
65 if (arch->nr_instructions_allocated == 0 && arch->instructions) in arch__grow_instructions()
68 new_nr_allocated = arch->nr_instructions_allocated + 128; in arch__grow_instructions()
69 new_instructions = realloc(arch->instructions, new_nr_allocated * sizeof(struct ins)); in arch__grow_instructions()
[all …]
/linux/drivers/usb/host/
H A Doxu210hp-hcd.c1 // SPDX-License-Identifier: GPL-2.0+
6 * This code is *strongly* based on EHCI-HCD code by David Brownell since
7 * the chip is a quasi-EHCI compatible.
26 #include <linux/dma-mapping.h>
83 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
86 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
102 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
111 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
117 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
118 u8 portroute[8]; /* nibbles for routing - offset 0xC */
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]