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/freebsd/sys/dev/clk/allwinner/
H A Dccu_a10.c106 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
107 CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1)
108 CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2)
109 CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3)
110 CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4)
111 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
112 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
113 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
114 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
115 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
[all …]
H A Dccu_a13.c103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
107 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
108 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
109 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
110 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
111 CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10)
112 CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13)
[all …]
H A Dccu_d1.c125 CCU_GATE(CLK_BUS_DE, "bus-de", "psi-ahb", 0x60C, 0)
126 CCU_GATE(CLK_BUS_DI, "bus-di", "psi-ahb", 0x62C, 0)
127 CCU_GATE(CLK_BUS_G2D, "bus-g2d", "psi-ahb", 0x63C, 0)
128 CCU_GATE(CLK_BUS_CE, "bus-ce", "psi-ahb", 0x68C, 0)
129 CCU_GATE(CLK_BUS_VE, "bus-ve", "psi-ahb", 0x690, 0)
130 CCU_GATE(CLK_BUS_DMA, "bus-dma", "psi-ahb", 0x70C, 0)
131 CCU_GATE(CLK_BUS_MSGBOX0, "bus-msgbox0", "psi-ahb", 0x71C, 0)
132 CCU_GATE(CLK_BUS_MSGBOX1, "bus-msgbox1", "psi-ahb", 0x71C, 1)
133 CCU_GATE(CLK_BUS_MSGBOX2, "bus-msgbox2", "psi-ahb", 0x71C, 2)
134 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "psi-ahb", 0x72C, 0)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.yaml251 - const: iface # Configuration AHB clock
262 - const: ahb # AHB reset
285 - const: iface # Configuration AHB clock
326 - const: ahb # AHB reset
327 - const: phy_ahb # PHY AHB reset
345 - const: ahb # AHB clock
358 - const: ahb # AHB reset
413 - const: ahb # AHB clock
425 - const: ahb # AHB Reset
457 - const: ahb # AHB Reset
[all …]
H A Dqcom,pcie.txt92 - "iface" Configuration AHB clock
127 - "ahb" AHB clock
144 - "iface" AHB clock
203 - "ahb" AHB reset
228 - "ahb" AHB reset
229 - "phy_ahb" PHY AHB reset
241 - "ahb" AHB Reset
253 - "ahb" AHB Reset
266 - "ahb" AHB reset
354 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
H A Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
H A Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
H A Dallwinner,sun9i-a80-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
7 title: Allwinner A80 AHB Clock
20 const: allwinner,sun9i-a80-ahb-clk
46 compatible = "allwinner,sun9i-a80-ahb-clk";
H A Dallwinner,sun4i-a10-gates-clk.yaml26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
100 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
102 clocks = <&ahb>;
H A Dqcom,ipq9574-cmn-pll.yaml38 - description: The AHB clock
42 Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
48 - const: ahb
74 clock-names = "ref", "ahb", "sys";
H A Dstarfive,jh7110-aoncrg.yaml24 - description: STG AXI/AHB
31 - description: STG AXI/AHB or GMAC0 RGMII RX
32 - description: APB Bus or STG AXI/AHB
40 - description: STG AXI/AHB
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,geni-se.yaml99 - const: s-ahb
103 - description: Slave AHB Clock
114 - const: m-ahb
115 - const: s-ahb
119 - description: Master AHB Clock
120 - description: Slave AHB Clock
136 clock-names = "m-ahb", "s-ahb";
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Darm-pl08x.txt15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
21 which AHB master that is used.
33 - dmas: List of DMA controller phandle, request channel and AHB master id
H A Dsnps-dma.txt9 - dma-masters: Number of AHB masters supported by the controller
16 - data-width: Maximum data width supported by hardware per AHB master
21 - data_width: Maximum data width supported by hardware per AHB master
28 - snps,dma-protection-control: AHB HPROT[3:1] protection setting.
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dintel,ixp4xx-ahb-queue-manager.yaml5 $id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dnvidia,tegra30-smmu.txt10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drockchip,vdec.yaml48 - description: The Video Decoder AHB interface clock
57 - const: ahb
69 - description: The Video Decoder AHB interface reset
77 - const: ahb
152 clock-names = "axi", "ahb", "cabac", "core";
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dallwinner,sun4i-a10-nand.yaml34 - const: ahb
41 const: ahb
100 clock-names = "ahb", "mod";
102 reset-names = "ahb";
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun6i-a31.dtsi294 clock-names = "ahb",
347 clock-names = "ahb",
395 clock-names = "ahb",
400 reset-names = "ahb";
416 clock-names = "ahb",
421 reset-names = "ahb";
437 clock-names = "ahb",
442 reset-names = "ahb";
456 clock-names = "ahb",
461 reset-names = "ahb";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml185 - const: ahb
204 - const: ahb
224 - const: ahb
245 - const: ahb
265 - const: ahb
389 clock-names = "ahb",
463 clock-names = "ahb",
532 clock-names = "ahb", "tcon-ch0";
582 clock-names = "ahb", "tcon-ch0";
637 clock-names = "ahb", "tcon-ch1";
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-ath79.txt6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
20 clock-names = "ahb";
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dgmu.yaml148 - description: GPU AHB clock
157 - const: ahb
212 - description: GPU AHB clock
219 - const: ahb
248 - description: GPU AHB clock
257 - const: ahb
H A Ddpu-sc7180.yaml33 - description: Display AHB clock from gcc
34 - description: Display AHB clock from dispcc
40 - const: ahb
96 - description: Display ahb clock
182 clock-names = "iface", "ahb", "core";

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