| /linux/Documentation/arch/arm64/ |
| H A D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
15 Some Armv9 SoCs suffer from a big.LITTLE misfeature where only a subset
16 of the CPUs are capable of executing 32-bit user applications. On such
17 a system, Linux by default treats the asymmetry as a "mismatch" and
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
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| /linux/Documentation/userspace-api/media/cec/ |
| H A D | cec-pin-error-inj.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 The CEC Pin Framework is a core CEC framework for CEC hardware that only
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
12 allows you to connect the CEC pin to a GPIO on e.g. a Raspberry Pi and
13 you have now made a CEC adapter.
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
29 The error injection commands are not a stable ABI and may change in the
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| /linux/drivers/gpio/ |
| H A D | gpio-104-idi-48.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
29 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
49 *mask = BIT(line); in idi_48_reg_mask_xlate()
91 .mask = BIT((_id) / 8), \
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
97 IDI48_REGMAP_IRQ(3), IDI48_REGMAP_IRQ(4), IDI48_REGMAP_IRQ(5), /* 3-5 */
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| /linux/drivers/net/wireless/ath/ath11k/ |
| H A D | rx_desc.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
89 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
90 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
91 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
92 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
93 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
94 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
95 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
96 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
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| /linux/arch/mips/lib/ |
| H A D | bitops.c | 6 * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
16 * __mips_set_bit - Atomically set a bit in memory. This is called by
17 * set_bit() if it cannot find a faster solution.
18 * @nr: the bit to set
23 volatile unsigned long *a = &addr[BIT_WORD(nr)]; in __mips_set_bit() local
24 unsigned int bit = nr % BITS_PER_LONG; in __mips_set_bit() local
28 mask = 1UL << bit; in __mips_set_bit()
30 *a |= mask; in __mips_set_bit()
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
38 * it cannot find a faster solution.
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| /linux/include/linux/ |
| H A D | math64.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
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| H A D | cnt32_to_63.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
17 /* this is used only to give gcc a clue about good code generation */
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
40 * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
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| /linux/drivers/net/fddi/skfp/h/ |
| H A D | skfbi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
31 * Note: The temperature and voltage sensors are relocated on a different
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
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| /linux/Documentation/userspace-api/media/rc/ |
| H A D | rc-protos.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
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| /linux/Documentation/staging/ |
| H A D | crc32.rst | 5 A CRC is a long-division remainder. You add the CRC to the message,
6 and the whole thing (message+CRC) is a multiple of the given
10 is used by a lot of hardware implementations, and is why so many
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
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| /linux/Documentation/driver-api/ |
| H A D | ioctl.rst | 18 the ioctl system call. While this can be any 32-bit number that uniquely
19 identifies an action for a particular driver, there are a number of
22 ``include/uapi/asm-generic/ioctl.h`` provides four macros for defining
28 The macro name specifies how the argument will be used. It may be a
31 argument or those passing an integer value instead of a pointer.
36 An 8-bit number, often a character literal, specific to a subsystem
37 or driver, and listed in Documentation/userspace-api/ioctl/ioctl-number.rst
40 An 8-bit number identifying the specific command, unique for a give
45 encodes the ``sizeof(data_type)`` value in a 13-bit or 14-bit integer,
46 leading to a limit of 8191 bytes for the maximum size of the argument.
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| /linux/Documentation/devicetree/bindings/powerpc/ |
| H A D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
28 It is implemented as a child of the node "/cpus", but this must not be
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
42 be extended in a backward compatible manner which would not warrant a
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| /linux/Documentation/networking/ |
| H A D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
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| /linux/include/uapi/linux/ |
| H A D | swab.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
124 * __swab64 - return a byteswapped 64-bit value
146 * __swahw32 - return a word-swapped 32-bit value
157 * __swahb32 - return a high and low byte-swapped 32-bit value
168 * __swab16p - return a byteswapped 16-bit value from a pointer
169 * @p: pointer to a naturally-aligned 16-bit value
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | rx_desc.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
14 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
15 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
16 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
17 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
18 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
19 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
20 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
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| /linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | bitfield.h | 5 * Author Copyright (c) Marc A. Viredaz, 1998
10 * Purpose Definition of macros to operate on bit fields.
29 * The macro "Fld" encodes a bit field, given its size and its shift value
30 * with respect to bit 0.
33 * A more intuitive way to encode bit fields would have been to use their
34 * mask. However, extracting size and shift value information from a bit
35 * field's mask is cumbersome and might break the assembler (255-character
36 * line-size limit).
39 * Size Size of the bit field, in number of bits.
40 * Shft Shift value of the bit field with respect to bit 0.
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| /linux/drivers/regulator/ |
| H A D | da9121-regulator.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
23 #include <dt-bindings/regulator/dlg,da9121-regulator.h>
48 * include a modification of these settings to match the required
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| /linux/drivers/media/i2c/ |
| H A D | max9271.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017-2020 Jacopo Mondi
4 * Copyright (C) 2017-2020 Kieran Bingham
5 * Copyright (C) 2017-2020 Laurent Pinchart
6 * Copyright (C) 2017-2020 Niklas Söderlund
26 #define MAX9271_R02_RES BIT(4)
30 #define MAX9271_SEREN BIT(7)
31 #define MAX9271_CLINKEN BIT(6)
32 #define MAX9271_PRBSEN BIT(5)
33 #define MAX9271_SLEEP BIT(4)
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| /linux/arch/riscv/include/asm/ |
| H A D | bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
19 #include <asm-generic/bitops/__ffs.h>
20 #include <asm-generic/bitops/__fls.h>
21 #include <asm-generic/bitops/ffs.h>
22 #include <asm-generic/bitops/fls.h>
30 #include <asm-generic/bitops/__ffs.h>
31 #include <asm-generic/bitops/__fls.h>
32 #include <asm-generic/bitops/ffs.h>
33 #include <asm-generic/bitops/fls.h>
35 #include <asm/alternative-macros.h>
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| /linux/drivers/media/cec/core/ |
| H A D | cec-pin-priv.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * cec-pin-priv.h - internal cec-pin header
13 #include <media/cec-pin.h>
16 ((pin && pin->ops->op && !pin->adap->devnode.unregistered) ? \
17 pin->ops->op(pin->adap, ## arg) : 0)
21 if (pin && pin->ops->op && \
22 !pin->adap->devnode.unregistered) \
23 pin->ops->op(pin->adap, ## arg); \
36 /* Low-drive was detected, wait for bus to go high */
38 /* Drive CEC low for the start bit */
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| /linux/Documentation/process/ |
| H A D | adding-syscalls.rst | 4 Adding a New System Call
7 This document describes what's involved in adding a new system call to the
9 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>`.
13 ------------------------
15 The first thing to consider when adding a new system call is whether one of
18 kernel, there are other possibilities -- choose what fits best for your
21 - If the operations involved can be made to look like a filesystem-like
22 object, it may make more sense to create a new filesystem or device. This
23 also makes it easier to encapsulate the new functionality in a kernel module
26 - If the new functionality involves operations where the kernel notifies
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| /linux/arch/m68k/ifpsp060/ |
| H A D | CHANGES | 3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
12 INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
31 ---------------------------
38 Inexact FPSR bit. Emulation now does not set Inexact for
42 mode was pre-decrement or post-increment and the address register
43 was A0 or A1, the address register was not being updated as a result
49 ---------
51 a failing value to the 68060SP, the package ignores
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| /linux/arch/x86/include/asm/ |
| H A D | sync_bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * These have to be done with inline assembly: that way the bit-setting
11 * is guaranteed to be atomic. All bit operations return 0 if the bit
14 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
22 * sync_set_bit - Atomically set a bit in memory
23 * @nr: the bit to set
30 * restricted to acting on a single-word quantity.
41 * sync_clear_bit - Clears a bit in memory
42 * @nr: Bit to clear
46 * not contain a memory barrier, so if it is used for locking purposes,
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| /linux/Documentation/bpf/standardization/ |
| H A D | instruction-set.rst | 9 referred to as BPF, is a technology with origins in the Linux kernel
10 that can run untrusted programs in a privileged context such as an
14 As a historical note, BPF originally stood for Berkeley Packet Filter,
16 no longer makes sense. BPF is now considered a standalone term that
27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
32 of types using a shorthand syntax and refers to several expository,
38 -----
40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
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| /linux/Documentation/devicetree/bindings/dma/stm32/ |
| H A D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
14 a phandle to the MDMA controller plus the following five integer cells:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
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