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/freebsd/sys/contrib/dev/iwlwifi/cfg/
H A D9000.c97 .d3_debug_data_length = 92 * 1024, \
163 const char iwl9162_160_name[] = "Intel(R) Wireless-AC 9162 160MHz";
164 const char iwl9260_160_name[] = "Intel(R) Wireless-AC 9260 160MHz";
165 const char iwl9270_160_name[] = "Intel(R) Wireless-AC 9270 160MHz";
166 const char iwl9461_160_name[] = "Intel(R) Wireless-AC 9461 160MHz";
167 const char iwl9462_160_name[] = "Intel(R) Wireless-AC 9462 160MHz";
168 const char iwl9560_160_name[] = "Intel(R) Wireless-AC 9560 160MHz";
171 "Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz";
175 "Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz";
179 "Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz";
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-st.txt41 - max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
97 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
/freebsd/sys/contrib/device-tree/Bindings/gpu/
H A Darm,mali-valhall-csf.yaml73 power coefficient in units of uW/MHz/V^2. The
84 where voltage is in V, frequency is in MHz.
122 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d-flex-concentrator.dts128 * ST chip maximum SPI clock frequency is 33 MHz.
131 * TPM shall support a SPI clock frequency range of 10-24 MHz.
208 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */
261 MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */
H A Dimx6ul-isiot.dtsi33 90 91 92 93 94 95 96 97 98 99
349 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
360 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
H A Dimx6ul-geam.dts34 90 91 92 93 94 95 96 97 98 99
413 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
424 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
H A Dimx6qdl-gw5903.dtsi70 90 91 92 93 94 95 96 97 98 99
683 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
713 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
726 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
755 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
771 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
H A Dimx6qdl-gw5910.dtsi234 channel@92 {
632 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
645 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15_a7.dts44 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
64 capacity-dmips-mhz = <516>;
74 capacity-dmips-mhz = <516>;
84 capacity-dmips-mhz = <516>;
203 interrupts = <0 92 4>,
245 /* Reference 24MHz clock */
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih410-clock.dtsi8 * Fixed 30MHz oscillator inputs to SoC
33 clockgen-a9@92b0000 {
H A Dstih418-clock.dtsi8 * Fixed 30MHz oscillator inputs to SoC
33 clockgen-a9@92b0000 {
H A Dstih407-clock.dtsi8 * Fixed 30MHz oscillator inputs to SoC
30 clockgen-a9@92b0000 {
H A Dste-nomadik-nhk15.dts229 /* 320 ns min period ~= 3 MHz */
259 90 91 92 93 94 95 96 97 98 99
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-nvm-parse.c90 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
99 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
151 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
152 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
153 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
154 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
183 * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
185 * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
189 * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
215 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz i
[all...]
/freebsd/contrib/ntp/scripts/stats/
H A DREADME.timecodes72 example: " 92 216 15:36:43.640 D"
125 F = current receive frequency (1-5 = 2.5, 5, 10, 15, 20 MHz)
/freebsd/contrib/file/magic/Magdir/
H A Driff12 # audio format tag. Assume limits: max 1024 bit, 128 channels, 1 MHz
615 >>>>(92.l+96) string LIST
616 >>>>>(92.l+104) string strlstrh
617 >>>>>>(92.l+116) string auds \b, audio:
619 >>>>>>>(92.l+172) string strf
620 >>>>>>>>(92.l+180) leshort 0x0001 uncompressed PCM
621 >>>>>>>>(92.l+180) leshort 0x0002 ADPCM
622 >>>>>>>>(92.l+180) leshort 0x0006 aLaw
623 >>>>>>>>(92.l+180) leshort 0x0007 uLaw
624 >>>>>>>>(92.l+180) leshort 0x0050 MPEG-1 Layer 1 or 2
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.c353 .freq = 4920, /* MHz */
361 .freq = 4930, /* MHz */
369 .freq = 4940, /* MHz */
377 .freq = 4950, /* MHz */
385 .freq = 4960, /* MHz */
393 .freq = 4970, /* MHz */
401 .freq = 4980, /* MHz */
409 .freq = 4990, /* MHz */
417 .freq = 5000, /* MHz */
425 .freq = 5010, /* MHz */
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-802_11.c430 * 0 for 20 MHz, 1 for 40 MHz;
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
441 { /* 20 Mhz */ { 13.0f, /* SGI */ 14.4f, },
442 /* 40 Mhz */ { 27.0f, /* SGI */ 30.0f, },
446 { /* 20 Mhz */ { 19.5f, /* SGI */ 21.7f, },
447 /* 40 Mhz */ { 40.5f, /* SGI */ 45.0f, },
451 { /* 20 Mhz */ { 26.0f, /* SGI */ 28.9f, },
452 /* 40 Mhz */ { 54.0f, /* SGI */ 60.0f, },
456 { /* 20 Mhz */ { 39.0f, /* SGI */ 43.3f, },
[all …]
/freebsd/share/doc/papers/timecounter/
H A Dtimecounter.ms240 A counter running on a 1 MHz frequency will have a resolution
661 2 sup{16} cdot {100 Hz} = 6.5536 MHz
664 Similarly, if the counter runs at 10MHz, the minimum HZ is
668 {10 MHz} over {2 sup{16}} = 152.6 Hz
855 The frequency chosen, 3.5795454... MHz\**
900 bit timecounter running at 100MHz was successfully implemented.
912 Using this setup, a standard 133 MHz Pentium based PC is able to
1043 Electrical Engineering Department Report 92-3-1, University of Delaware, March 1992, 63 pp.
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra186-clock.h460 #define TEGRA186_CLK_I2C_SLOW 92
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
/freebsd/contrib/wpa/wpa_supplicant/
H A DREADME-HS20478 <3>SME: Trying to authenticate with 02:00:00:00:01:00 (SSID='Example Network' freq=2412 MHz)
479 <3>Trying to associate with 02:00:00:00:01:00 (SSID='Example Network' freq=2412 MHz)
519 <3>SME: Trying to authenticate with 02:00:00:00:01:00 (SSID='Example Network' freq=2412 MHz)
520 <3>Trying to associate with 02:00:00:00:01:00 (SSID='Example Network' freq=2412 MHz)
586 noise=-92
/freebsd/sys/net80211/
H A Dieee80211.h788 #define IEEE80211_HTCAP_SHORTGI20 0x0020 /* Short GI in 20MHz */
789 #define IEEE80211_HTCAP_SHORTGI40 0x0040 /* Short GI in 40MHz */
800 #define IEEE80211_HTCAP_DSSSCCK40 0x1000 /* DSSS/CCK in 40MHz */
802 #define IEEE80211_HTCAP_40INTOLERANT 0x4000 /* 40MHz intolerant */
867 #define IEEE80211_HTINFO_TXWIDTH_20 0x00 /* 20MHz width */
950 IEEE80211_VHT_CHANWIDTH_USE_HT = 0, /* 20 MHz or 40 MHz */
951 IEEE80211_VHT_CHANWIDTH_80MHZ = 1, /* 80MHz */
952 IEEE80211_VHT_CHANWIDTH_160MHZ = 2, /* 160MHz */
953 IEEE80211_VHT_CHANWIDTH_80P80MHZ = 3, /* 80+80MHz */
1064 * 0 - 20 MHz
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3660.dtsi65 capacity-dmips-mhz = <592>;
79 capacity-dmips-mhz = <592>;
92 capacity-dmips-mhz = <592>;
105 capacity-dmips-mhz = <592>;
118 capacity-dmips-mhz = <1024>;
132 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
158 capacity-dmips-mhz = <1024>;
699 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm6125.dtsi45 capacity-dmips-mhz = <1024>;
59 capacity-dmips-mhz = <1024>;
68 capacity-dmips-mhz = <1024>;
77 capacity-dmips-mhz = <1024>;
86 capacity-dmips-mhz = <1638>;
100 capacity-dmips-mhz = <1638>;
109 capacity-dmips-mhz = <1638>;
118 capacity-dmips-mhz = <1638>;
1447 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5112.c73 * Take the MHz channel value and set the Channel value
99 "%s: invalid channel %u MHz\n", in ar5112SetChannel()
117 freq = freq - 2; /* Align to even 5MHz raster */ in ar5112SetChannel()
134 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n", in ar5112SetChannel()
287 ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 92, 2); in ar5112SetRfRegs()

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