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/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
68 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
[all …]
H A Dintel.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
39 * Processors which have self-snooping capability can handle conflicting
47 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
79 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
81 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
103 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
104 * - https://kb.vmware.com/s/article/52345
105 * - Microcode revisions observed in the wild
106 * - Release note from 20180108 microcode release
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/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
87 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2 8 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
164 /* v0 now have sets per way, multiply it by line size now
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/linux/arch/arm/mm/
H A Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
17 #define CACHE_WAY_PER_SET 8
19 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
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/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
35 #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
49 #define SPR_PCCFGR (SPRGROUP_SYS + 8)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
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/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
13 8 = /dev/random Nondeterministic random number gen.
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
67 8 = /dev/fd?h1200 5.25" 1200K in a 1200K drive(1)
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/linux/Documentation/arch/x86/
H A Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
28 either way.
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
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/linux/arch/mips/mm/
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
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/linux/tools/testing/selftests/net/forwarding/
H A DREADME9 (dev->netns_local) and most of them probably do not support the
10 L1-separation provided by namespaces.
17 vrf-h1 | vrf-h2
18 + +---+----+ +
24 +--------+ +--------+
37 between 4-ports LAGs or 8-way ECMP requires many physical links that are
38 not always available. With the VRF-based approach one merely needs to
65 various ways. A number of these variables can be overridden. The way these
75 One way of overriding these variables is through the environment:
80 way to pass it through the environment. Its value can instead be given as
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/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
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/linux/arch/arm/include/asm/
H A Dv7m.h1 /* SPDX-License-Identifier: GPL-2.0 */
49 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
50 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
62 /* Memory-mapped MPU registers for M-class */
75 #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
76 #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
81 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
82 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
83 #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
84 #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
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H A Duser.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Core file format: The core file is written in such a way that gdb
9 linux we use the 'trad-core' bfd). There are quite a number of
21 DATA: The data area is stored. We use current->end_text to
22 current->brk to pick up all of the user variables, plus any memory
24 is demand-zero or if a page is totally unused, we just cover the entire
25 range. All of the addresses are rounded in such a way that an integral
29 current->start_stack, so we round each of these off in order to be able
43 } fpregs[8];
46 unsigned char ftype[8];
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/linux/arch/x86/crypto/
H A Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
57 * 1-way blowfish
83 movq p+4*(n-1)(CTX), RT0; \
120 round_enc(8);
166 4-way blowfish, four blocks parallel
169 /* F() for 4-way. Slower when used alone/1-way, but faster when used
170 * parallel/4-way (tested on AMD Phenom II & Intel Xeon E7330).
212 movq p+4*((n)-1)(CTX), RKEY; \
217 preload_roundkey_dec(n - 2);
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
78 CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
137 CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8,
183 * Return the L2 Cache way partitioning for a given core.
189 * -1 on error
199 * a way, while a 1 bit blocks the core from evicting any
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-l2c.c7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-l2c.h>
37 #include <asm/octeon/cvmx-spinlock.h>
43 * NOTE: This only protects calls from within a single application -
55 return -1; in cvmx_l2c_get_core_way_partition()
64 field = (core & 0x3) * 8; in cvmx_l2c_get_core_way_partition()
89 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; in cvmx_l2c_set_core_way_partition()
95 return -1; in cvmx_l2c_set_core_way_partition()
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/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/linux/sound/soc/google/
H A Dchv3-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * The I2S interface consists of two ring buffers - one for RX and one for
11 * on which way the data is flowing, either the software or the hardware
16 * (see chv3_dma_ack). This seems to be the only way to reliably obtain
21 * will wait for the consumer index to move out of the way. With playback,
24 * would have to wait for the consumer index to move out of the way by
25 * busy-waiting, which would keep stalling the kernel for quite a long time.
29 * way, ALSA will not try to fill up the entire buffer, and all callbacks
30 * are wait-free.
70 .name = "chv3-i2s",
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/linux/arch/x86/include/asm/
H A Duser_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Core file format: The core file is written in such a way that gdb
8 linux we use the 'trad-core' bfd). There are quite a number of
20 DATA: The data area is stored. We use current->end_text to
21 current->brk to pick up all of the user variables, plus any memory
23 is demand-zero or if a page is totally unused, we just cover the entire
24 range. All of the addresses are rounded in such a way that an integral
28 current->start_stack, so we round each of these off in order to be able
38 * interacting with the FXSR-format floating point environment. Floating
53 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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H A Dmc146818rtc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 * a non-SMP machine just to mark that the lock is owned.
30 * This only works with compare-and-swap. There is no other way to
44 new = ((smp_processor_id() + 1) << 8) | reg; in lock_cmos()
62 return (cmos_lock >> 8) == (smp_processor_id() + 1); in do_i_have_lock_cmos()
91 * an ISA port access but the way to access the date register differs ...
101 #define RTC_IRQ 8
/linux/Documentation/i2c/
H A Dsmbus-protocol.rst46 Comm (8 bits) Command byte, a data byte which often selects a register on
48 Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and
50 Count (8 bits) A data byte containing the length of a block operation.
124 available for reads where the two data bytes are the other way
158 available for writes where the two data bytes are the other way
207 SMBus Block Write - Block Read Process Call
210 SMBus Block Write - Block Read Process Call was introduced in
234 This is implemented in the following way in the Linux kernel:
241 client->irq assigned to a Host Notify IRQ if no one else specified another.
243 There is currently no way to retrieve the data parameter from the client.
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/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
53 #define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
68 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
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/linux/Documentation/trace/
H A Ddebugging.rst11 - Written for: 6.12
14 ------------
21 $ sudo mount -t tracefs tracefs /sys/kernel/tracing
25 --------------------
30 written to the tracing ring buffer in a lockless way. To make it even
33 arguments will be post processed when the ring buffer is read. This way the
57 ------------------------
77 buffers is broken up into sub-buffers that are by default PAGE_SIZE. The
79 so, on a machine with 8 CPUs, that's actually 400K total.
82 -------------------------------
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