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/linux/lib/zstd/compress/
H A Dclevels.h5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
17 /*-===== Pre-defined compression levels =====-*/
24 { /* "default" - for any srcSize > 256 KB */
27 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
28 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
29 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
30 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
31 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
32 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6 */
[all …]
/linux/drivers/platform/x86/intel/speed_select_if/
H A Disst_tpmi_core.c1 // SPDX-License-Identifier: GPL-2.0-only
49 #define SST_REG_SIZE 8
52 * struct sst_header - SST main header
56 * Bit[8]= SST_CP enable (1), disable (0)
59 * @cp_offset: Qword (8 bytes) offset to the SST_CP register bank
60 * @pp_offset: Qword (8 bytes) offset to the SST_PP register bank
63 * This register allows SW to discover SST capability and the offsets to SST-CP
64 * and SST-PP register banks.
75 * struct cp_header - SST-CP (core-power) header
76 * @feature_id: 0=SST-CP, 1=SST-PP, 2=SST-BF, 3=SST-TF
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
55 #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8
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/linux/net/netfilter/
H A Dnf_conntrack_h323_asn1.c1 // SPDX-License-Identifier: GPL-2.0-only
51 #define BMPSTR 8
60 /* #define BITS 1-8 */
72 #define OPEN 8
100 #define INC_BIT(bs) if((++(bs)->bit)>7){(bs)->cur++;(bs)->bit=0;}
101 #define INC_BITS(bs,b) if(((bs)->bit+=(b))>7){(bs)->cur+=(bs)->bit>>3;(bs)->bit&=7;}
102 #define BYTE_ALIGN(bs) if((bs)->bit){(bs)->cur++;(bs)->bit=0;}
110 static int decode_nul(struct bitstr *bs, const struct field_t *f, char *base, int level);
111 static int decode_bool(struct bitstr *bs, const struct field_t *f, char *base, int level);
112 static int decode_oid(struct bitstr *bs, const struct field_t *f, char *base, int level);
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/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
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/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c1 // SPDX-License-Identifier: MIT
47 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
48 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
49 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
50 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
51 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
53 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
54 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
55 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
56 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
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/linux/arch/powerpc/include/asm/
H A Dexception-64e.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Definitions for use by exception code on Book3-E
24 * the above re-entrancy issue.
27 * SPRGs are user-readable though, thus we might have to change some of
41 #define EX_R1 (0 * 8)
42 #define EX_CR (1 * 8)
43 #define EX_R10 (2 * 8)
44 #define EX_R11 (3 * 8)
45 #define EX_R14 (4 * 8)
46 #define EX_R15 (5 * 8)
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/linux/arch/arc/include/asm/
H A Dpgtable-levels.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
19 * -------------------------------------------------------
20 * | | <---------- PGDIR_SHIFT ----------> |
21 * | | | <-- PAGE_SHIFT --> |
22 * -------------------------------------------------------
24 * | | --> off in page frame
25 * | ---> index into Page Table
26 * ----> index into Page Directory
28 * Given software walk, the vaddr split is arbitrary set to 11:8:13
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/linux/tools/testing/selftests/kvm/lib/riscv/
H A Dprocessor.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V code
31 return (v + vm->page_size) & ~(vm->page_size - 1); in page_align()
59 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) in pte_index() argument
61 TEST_ASSERT(level > - in pte_index()
85 int level = vm->pgtable_levels - 1; virt_arch_pg_map() local
129 int level = vm->pgtable_levels - 1; addr_arch_gva2gpa() local
156 pte_dump(FILE * stream,struct kvm_vm * vm,uint8_t indent,uint64_t page,int level) pte_dump() argument
179 int level = vm->pgtable_levels - 1; virt_arch_dump() local
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/linux/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/
H A Dctrl90f1.h4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
7 …* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights rese…
8 * SPDX-License-Identifier: MIT
31 …06U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPA…
35 * [in] GPU sub-device handle - this API only supports unicast.
41 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
46 * [in] Page size (VA coverage) of the level to reserve.
47 * This need not be a leaf (page table) page size - it can be
48 * the coverage of an arbitrary level (including root page directory).
50 NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
[all …]
/linux/tools/power/x86/intel-speed-select/
H A Disst-core-mbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features for Mailbox Interface
26 static char *mbox_get_trl_level_name(int level) in mbox_get_trl_level_name() argument
31 if (level >= MAX_TRL_LEVELS_EMR) in mbox_get_trl_level_name()
34 snprintf(level_str, sizeof(level_str), "level-%d", level); in mbox_get_trl_level_name()
38 switch (level) { in mbox_get_trl_level_name()
66 if (id->cpu < 0) in mbox_is_punit_valid()
69 if (id->pkg < 0 || id->die < 0 || id->punit) in mbox_is_punit_valid()
88 err(-1, "%s open failed", pathname); in _send_mmio_command()
101 if (ioctl(fd, cmd, &io_regs) == -1) { in _send_mmio_command()
[all …]
H A Disst-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features
13 if (!isst_ops || !isst_ops->_name) { \
35 return -1; in isst_set_platform_ops()
43 isst_ops->update_platform_param(param, value); in isst_update_platform_param()
49 return isst_ops->get_disp_freq_multiplier(); in isst_get_disp_freq_multiplier()
55 return isst_ops->get_trl_max_levels(); in isst_get_trl_max_levels()
58 char *isst_get_trl_level_name(int level) in isst_get_trl_level_name() argument
61 return isst_ops->get_trl_level_name(level); in isst_get_trl_level_name()
67 return isst_ops->is_punit_valid(id); in isst_is_punit_valid()
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/linux/drivers/block/drbd/
H A Ddrbd_vli.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 -*- linux-c -*-
7 Copyright (C) 2001-2008, LINBIT Information Technologies GmbH.
8 Copyright (C) 1999-2008, Philipp Reisner <philipp.reisner@linbit.com>.
9 Copyright (C) 2002-2008, Lars Ellenberg <lars.ellenberg@linbit.com>.
19 * and possibly small-bandwidth replication,
55 * * simple byte-based
72 * starts as unary encoding the level, then modified so that
73 * 10 levels can be described in 8bit, with minimal overhead
77 * last level (+1 data bit, so it makes 64bit total). The only worse code when
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
33 XHCI controller#0 -- usb2phy -- phy#0
[all …]
/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
85 #define RX_THRESH_DFLT 8
86 #define TX_THRESH_DFLT 8
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
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/linux/scripts/gdb/linux/
H A Dpgtable.py1 # SPDX-License-Identifier: GPL-2.0-only
18 def page_mask(level=1): argument
20 if level == 1:
23 elif level == 2:
26 elif level == 3:
29 raise Exception(f'Unknown page level: {level}')
44 return (bit_start, bit_end), data >> bit_start & ((1 << (1 + bit_end - bit_start)) - 1)
46 def entry_va(level, phys_addr, translating_va): argument
47 def start_bit(level): argument
48 if level == 5:
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/linux/drivers/s390/net/
H A Dctcm_dbug.c1 // SPDX-License-Identifier: GPL-2.0
25 [CTCM_DBF_SETUP] = {"ctc_setup", 8, 1, 64, CTC_DBF_INFO, NULL},
26 [CTCM_DBF_ERROR] = {"ctc_error", 8, 1, 64, CTC_DBF_ERROR, NULL},
27 [CTCM_DBF_TRACE] = {"ctc_trace", 8, 1, 64, CTC_DBF_ERROR, NULL},
28 [CTCM_DBF_MPC_SETUP] = {"mpc_setup", 8, 1, 80, CTC_DBF_INFO, NULL},
29 [CTCM_DBF_MPC_ERROR] = {"mpc_error", 8, 1, 80, CTC_DBF_ERROR, NULL},
30 [CTCM_DBF_MPC_TRACE] = {"mpc_trace", 8, 1, 80, CTC_DBF_ERROR, NULL},
53 return -ENOMEM; in ctcm_register_dbf_views()
58 /* set a passing level */ in ctcm_register_dbf_views()
59 debug_set_level(ctcm_dbf[x].id, ctcm_dbf[x].level); in ctcm_register_dbf_views()
[all …]
/linux/arch/s390/kernel/
H A Dlgr.c1 // SPDX-License-Identifier: GPL-2.0
20 #define VM_LEVEL_MAX 2 /* Maximum is 8, but we only record two levels */
28 /* Level of system (1 = CEC, 2 = LPAR, 3 = z/VM */
29 u32 level; member
30 /* Level 1: CEC info (stsi 1.1.1) */
36 /* Level 2: LPAR info (stsi 2.2.2) */
38 char name[8];
39 /* Level
118 int level; lgr_info_get() local
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/linux/arch/mips/include/asm/sn/
H A Dfru.h8 * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
14 #define MAX_DIMMS 8 /* max # of dimm banks */
15 #define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
20 confidence_t km_confidence; /* confidence level that the memory is bad
24 /* confidence level that dimm[i] is bad
31 confidence_t kc_confidence; /* confidence level that cpu is bad */
32 confidence_t kc_icache; /* confidence level that instr. cache is bad */
33 confidence_t kc_dcache; /* confidence level that data cache is bad */
34 confidence_t kc_scache; /* confidence level that sec. cache is bad */
[all …]
/linux/Documentation/devicetree/bindings/power/supply/
H A Ddlg,da9150-fuel-gauge.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/dlg,da9150-fuel-gauge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA9150 Fuel-Gauge Power Supply
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
17 const: dlg,da9150-fuel-gauge
19 dlg,update-interval:
21 description: Interval time (milliseconds) between battery level checks.
[all …]
/linux/sound/soc/sof/xtensa/
H A Dcore.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
14 #include "../sof-priv.h"
23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
39 {8, "PrivilegedCause",
54 "An instruction fetch referenced a virtual address at a ring level less than CRING"},
62 "A load or store referenced a virtual address at a ring level less than CRING"},
84 static void xtensa_dsp_oops(struct snd_sof_dev *sdev, const char *level, void *oops) in xtensa_dsp_oops() argument
89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); in xtensa_dsp_oops()
91 if (xtensa_exception_causes[i].id == xoops->exccause) { in xtensa_dsp_oops()
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/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
51 #define IS_REG_2ND_BANK(x) ((x) >= 8)
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-controls:
24 .. _mpeg-control-id:
27 -----------------
35 .. _v4l2-mpeg-stream-type:
40 enum v4l2_mpeg_stream_type -
41 The MPEG-1, -2 or -4 output stream type. One cannot assume anything
48 .. flat-table::
49 :header-rows: 0
50 :stub-columns: 0
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/linux/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
24 #define AR5008_OFDM_RATES 8
25 #define AR5008_HT_SS_RATES 8
26 #define AR5008_HT_DS_RATES 8
32 #define AR5008_11NA_HT_SS_SHIFT 8
91 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
92 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
97 for (r = 0; r < array->ia_rows; r++) { in ar5008_write_bank6()
106 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
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