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/linux/lib/zstd/compress/
H A Dclevels.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
18 /*-===== Pre-defined compression levels =====-*/
25 { /* "default" - for any srcSize > 256 KB */
28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
32 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
[all …]
H A Dzstd_preSplit.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
22 #define THRESHOLD_BASE (THRESHOLD_PENALTY_RATE - 2)
28 #define HASHMASK (HASHTABLESIZE - 1)
31 /* for hashLog > 8, hash 2 bytes.
32 * for hashLog == 8, just take the byte, no hashing.
33 * The speed of this method relies on compile-time constant propagation */
36 assert(hashLog >= 8); in hash2()
37 if (hashLog == 8) return (U32)((const BYTE*)p)[0]; in hash2()
[all …]
/linux/drivers/platform/x86/intel/speed_select_if/
H A Disst_tpmi_core.c1 // SPDX-License-Identifier: GPL-2.0-only
51 #define SST_REG_SIZE 8
54 * struct sst_header - SST main header
58 * Bit[8]= SST_CP enable (1), disable (0)
61 * @cp_offset: Qword (8 bytes) offset to the SST_CP register bank
62 * @pp_offset: Qword (8 bytes) offset to the SST_PP register bank
65 * This register allows SW to discover SST capability and the offsets to SST-CP
66 * and SST-PP register banks.
77 * struct cp_header - SST-CP (core-power) header
78 * @feature_id: 0=SST-CP, 1=SST-PP, 2=SST-BF, 3=SST-TF
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
55 #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8
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/linux/net/netfilter/
H A Dnf_conntrack_h323_asn1.c1 // SPDX-License-Identifier: GPL-2.0-only
51 #define BMPSTR 8
60 /* #define BITS 1-8 */
72 #define OPEN 8
100 #define INC_BIT(bs) if((++(bs)->bit)>7){(bs)->cur++;(bs)->bit=0;}
101 #define INC_BITS(bs,b) if(((bs)->bit+=(b))>7){(bs)->cur+=(bs)->bit>>3;(bs)->bit&=7;}
102 #define BYTE_ALIGN(bs) if((bs)->bit){(bs)->cur++;(bs)->bit=0;}
110 static int decode_nul(struct bitstr *bs, const struct field_t *f, char *base, int level);
111 static int decode_bool(struct bitstr *bs, const struct field_t *f, char *base, int level);
112 static int decode_oid(struct bitstr *bs, const struct field_t *f, char *base, int level);
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/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
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/linux/arch/powerpc/include/asm/
H A Dexception-64e.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Definitions for use by exception code on Book3-E
24 * the above re-entrancy issue.
27 * SPRGs are user-readable though, thus we might have to change some of
41 #define EX_R1 (0 * 8)
42 #define EX_CR (1 * 8)
43 #define EX_R10 (2 * 8)
44 #define EX_R11 (3 * 8)
45 #define EX_R14 (4 * 8)
46 #define EX_R15 (5 * 8)
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/linux/tools/testing/selftests/kvm/lib/loongarch/
H A Dprocessor.c1 // SPDX-License-Identifier: GPL-2.0
15 static uint64_t virt_pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) in virt_pte_index() argument
20 shift = level * (vm->page_shift - 3) + vm->page_shift; in virt_pte_index()
21 mask = (1UL << (vm->page_shift - 3)) - 1; in virt_pte_index()
27 return entry & ~((0x1UL << vm->page_shift) - 1); in pte_addr()
32 return 1 << (vm->page_shift - 3); in ptrs_per_pte()
41 ptrs_per_pte = 1 << (vm->page_shift - 3); in virt_set_pgtable()
51 if (vm->pgd_created) in virt_arch_pgd_alloc()
55 for (i = 0; i < vm->pgtable_levels; i++) { in virt_arch_pgd_alloc()
58 vm->memslots[MEM_REGION_PT]); in virt_arch_pgd_alloc()
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/linux/arch/arc/include/asm/
H A Dpgtable-levels.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
19 * -------------------------------------------------------
20 * | | <---------- PGDIR_SHIFT ----------> |
21 * | | | <-- PAGE_SHIFT --> |
22 * -------------------------------------------------------
24 * | | --> off in page frame
25 * | ---> index into Page Table
26 * ----> index into Page Directory
28 * Given software walk, the vaddr split is arbitrary set to 11:8:13
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/linux/tools/testing/selftests/kvm/lib/riscv/
H A Dprocessor.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V code
31 return (v + vm->page_size) & ~(vm->page_size - 1); in page_align()
59 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) in pte_index() argument
61 TEST_ASSERT(level > -1, in pte_index()
62 "Negative page table level (%d) not possible", level); in pte_index()
63 TEST_ASSERT(level < vm->pgtable_levels, in pte_index()
64 "Invalid page table level (%d)", level); in pte_index()
66 return (gva & pte_index_mask[level]) >> pte_index_shift[level]; in pte_index()
71 size_t nr_pages = page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size; in virt_arch_pgd_alloc()
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/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dvirtual-memory.json3 … the number of page walks initiated by a demand load that missed the first and second level TLBs.",
12 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 …licDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
32 "Counter": "0,1,2,3,4,5,6,7,8,9",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 "Counter": "0,1,2,3,4,5,6,7,8,9",
73 "Counter": "0,1,2,3,4,5,6,7,8,9",
83 "Counter": "0,1,2,3,4,5,6,7,8,9",
93 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux/tools/power/x86/intel-speed-select/
H A Disst-core-mbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features for Mailbox Interface
26 static char *mbox_get_trl_level_name(int level) in mbox_get_trl_level_name() argument
31 if (level >= MAX_TRL_LEVELS_EMR) in mbox_get_trl_level_name()
34 snprintf(level_str, sizeof(level_str), "level-%d", level); in mbox_get_trl_level_name()
38 switch (level) { in mbox_get_trl_level_name()
66 if (id->cpu < 0) in mbox_is_punit_valid()
69 if (id->pkg < 0 || id->die < 0 || id->punit) in mbox_is_punit_valid()
88 err(-1, "%s open failed", pathname); in _send_mmio_command()
101 if (ioctl(fd, cmd, &io_regs) == -1) { in _send_mmio_command()
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H A Disst-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features
13 if (!isst_ops || !isst_ops->_name) { \
35 return -1; in isst_set_platform_ops()
43 isst_ops->update_platform_param(param, value); in isst_update_platform_param()
49 return isst_ops->get_disp_freq_multiplier(); in isst_get_disp_freq_multiplier()
55 return isst_ops->get_trl_max_levels(); in isst_get_trl_max_levels()
58 char *isst_get_trl_level_name(int level) in isst_get_trl_level_name() argument
61 return isst_ops->get_trl_level_name(level); in isst_get_trl_level_name()
67 return isst_ops->is_punit_valid(id); in isst_is_punit_valid()
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/linux/drivers/block/drbd/
H A Ddrbd_vli.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 -*- linux-c -*-
7 Copyright (C) 2001-2008, LINBIT Information Technologies GmbH.
8 Copyright (C) 1999-2008, Philipp Reisner <philipp.reisner@linbit.com>.
9 Copyright (C) 2002-2008, Lars Ellenberg <lars.ellenberg@linbit.com>.
19 * and possibly small-bandwidth replication,
55 * * simple byte-based
72 * starts as unary encoding the level, then modified so that
73 * 10 levels can be described in 8bit, with minimal overhead
77 * last level (+1 data bit, so it makes 64bit total). The only worse code when
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
33 XHCI controller#0 -- usb2phy -- phy#0
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/linux/drivers/s390/net/
H A Dctcm_dbug.c1 // SPDX-License-Identifier: GPL-2.0
25 [CTCM_DBF_SETUP] = {"ctc_setup", 8, 1, 64, CTC_DBF_INFO, NULL},
26 [CTCM_DBF_ERROR] = {"ctc_error", 8, 1, 64, CTC_DBF_ERROR, NULL},
27 [CTCM_DBF_TRACE] = {"ctc_trace", 8, 1, 64, CTC_DBF_ERROR, NULL},
28 [CTCM_DBF_MPC_SETUP] = {"mpc_setup", 8, 1, 80, CTC_DBF_INFO, NULL},
29 [CTCM_DBF_MPC_ERROR] = {"mpc_error", 8, 1, 80, CTC_DBF_ERROR, NULL},
30 [CTCM_DBF_MPC_TRACE] = {"mpc_trace", 8, 1, 80, CTC_DBF_ERROR, NULL},
53 return -ENOMEM; in ctcm_register_dbf_views()
58 /* set a passing level */ in ctcm_register_dbf_views()
59 debug_set_level(ctcm_dbf[x].id, ctcm_dbf[x].level); in ctcm_register_dbf_views()
[all …]
/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
57 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
85 #define RX_THRESH_DFLT 8
86 #define TX_THRESH_DFLT 8
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
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/linux/scripts/gdb/linux/
H A Dpgtable.py1 # SPDX-License-Identifier: GPL-2.0-only
18 def page_mask(level=1): argument
20 if level == 1:
23 elif level == 2:
26 elif level == 3:
29 raise Exception(f'Unknown page level: {level}')
46 entry_va(level, phys_addr, translating_va) global() argument
47 start_bit(level) global() argument
89 __init__(self, address, level) global() argument
154 page_size_line(ps_bit, ps, level) global() argument
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/linux/arch/mips/include/asm/sn/
H A Dfru.h8 * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
14 #define MAX_DIMMS 8 /* max # of dimm banks */
15 #define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
20 confidence_t km_confidence; /* confidence level that the memory is bad
24 /* confidence level that dimm[i] is bad
31 confidence_t kc_confidence; /* confidence level that cpu is bad */
32 confidence_t kc_icache; /* confidence level that instr. cache is bad */
33 confidence_t kc_dcache; /* confidence level that data cache is bad */
34 confidence_t kc_scache; /* confidence level that sec. cache is bad */
[all …]
/linux/Documentation/devicetree/bindings/power/supply/
H A Ddlg,da9150-fuel-gauge.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/dlg,da9150-fuel-gauge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA9150 Fuel-Gauge Power Supply
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
17 const: dlg,da9150-fuel-gauge
19 dlg,update-interval:
21 description: Interval time (milliseconds) between battery level checks.
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/linux/sound/soc/sof/xtensa/
H A Dcore.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
14 #include "../sof-priv.h"
23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},
39 {8, "PrivilegedCause",
54 "An instruction fetch referenced a virtual address at a ring level less than CRING"},
62 "A load or store referenced a virtual address at a ring level less than CRING"},
84 static void xtensa_dsp_oops(struct snd_sof_dev *sdev, const char *level, void *oops) in xtensa_dsp_oops() argument
89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); in xtensa_dsp_oops()
91 if (xtensa_exception_causes[i].id == xoops->exccause) { in xtensa_dsp_oops()
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/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
51 #define IS_REG_2ND_BANK(x) ((x) >= 8)
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
24 #define AR5008_OFDM_RATES 8
25 #define AR5008_HT_SS_RATES 8
26 #define AR5008_HT_DS_RATES 8
32 #define AR5008_11NA_HT_SS_SHIFT 8
91 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
92 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
97 for (r = 0; r < array->ia_rows; r++) { in ar5008_write_bank6()
106 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
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/linux/arch/mips/kernel/
H A Dirq_txx9.c6 * Copyright 2001, 2003-2005 MontaVista Software Inc.
10 * Copyright (C) 2000-2001 Toshiba Corporation
26 u32 ilr[8];
62 unsigned char level; member
68 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; in txx9_irq_unmask()
69 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2]; in txx9_irq_unmask()
70 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8; in txx9_irq_unmask()
73 | (txx9irq[irq_nr].level << ofs), in txx9_irq_unmask()
79 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; in txx9_irq_mask()
80 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2]; in txx9_irq_mask()
[all …]

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