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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
36 debounce-interval = <0>;
[all …]
H A Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include "exynos5422-odroid-core.dtsi"
16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 led-controller {
20 compatible = "pwm-leds";
22 led-1 {
26 pwm-names = "pwm2";
27 max-brightness = <255>;
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
19 cpu-map {
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
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H A Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
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H A Dhi3660.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
[all …]
/freebsd/sys/amd64/include/
H A Dpcpu.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 char padding[128 - (2 * sizeof(int))];
53 * to each CPU's data can be set up for things like "check curproc on all
58 struct pcpu *pc_prvspace; /* Self-reference */ \
60 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \
69 u_int pc_acpi_id; /* ACPI CPU i
276 zpcpu_offset_cpu(cpu) global() argument
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp1 //===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // for RISC-V CPUs.
12 //===----------------------------------------------------------------------===//
46 static const CPUInfo *getCPUInfoByName(StringRef CPU) { in getCPUInfoByName() argument
48 if (C.Name == CPU) in getCPUInfoByName()
53 bool hasFastScalarUnalignedAccess(StringRef CPU) { in hasFastScalarUnalignedAccess() argument
54 const CPUInfo *Info = getCPUInfoByName(CPU); in hasFastScalarUnalignedAccess()
55 return Info && Info->FastScalarUnalignedAccess; in hasFastScalarUnalignedAccess()
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/freebsd/share/man/man7/
H A Darch.71 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
32 .Nd Architecture-specific details
34 Differences between CPU architectures and platforms supported by
40 For full details consult the processor-specific ABI supplement
83 This table shows currently supported CPU architectures along with the first
86 .Bl -column -offset indent "Architecture" "Initial Release"
100 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
128 .Bl -tag -width "Dv ILP32"
133 types machine representations all have 4-byte size.
141 are 8 bytes.
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/freebsd/sys/dts/arm64/overlays/
H A Dsun50i-h5-opp.dtso1 /dts-v1/;
4 #include <dt-bindings/clock/sun8i-h3-ccu.h>
7 compatible = "allwinner,sun50i-h5";
12 compatible = "operating-points-v2";
13 opp-shared;
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <1000000 1000000 1300000>;
18 clock-latency-ns = <244144>; /* 8 32k periods */
22 opp-hz = /bits/ 64 <648000000>;
23 opp-microvolt = <1040000 1040000 1300000>;
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/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
[all …]
/freebsd/share/man/man4/man4.i386/
H A Dapm.430 .Bl -enum -offset indent
39 .Xr syslogd 8
43 slows CPU clock when there are no system activities (runnable processes,
46 supports CPU idling.
56 .Bl -tag -width 4n -offset indent
71 (Halt CPU until an interrupt occurs)
73 .Dq Em Idle CPU
77 .Dq Em Idle CPU
85 .Dq Em Idle CPU .
86 On some implementations that do not support CPU clock slowdown, APM
[all …]
/freebsd/share/man/man4/
H A Dhwpmc.41 .\" Copyright (c) 2003-2008 Joseph Koshy
31 .Dd July 8, 2023
39 .Bd -ragged -offset indent
44 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
54 .Bd -ragged -offset indent
62 .Bd -ragged -offset indent
75 The driver supports multi-processor systems.
89 .Bl -tag -width ".Em Process-scope"
90 .It Em "Process-scope"
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H A Dsmp.429 .Nd description of the FreeBSD Symmetric Multi-Processor kernel
35 kernel implements symmetric multi-processor support.
43 the read-only sysctl variable
46 The number of online threads per CPU core is available in the read-only sysctl
49 The number of physical CPU cores detected by the system is available in the
50 read-only sysctl variable
54 allows specific CPUs on a multi-processor system to be disabled.
57 tunable, where X is the APIC ID of a CPU.
58 Setting this tunable to 1 will result in the corresponding CPU being
69 scheduler implements CPU topology detection and adjusts the scheduling
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H A Dcpufreq.430 .Nd CPU frequency control framework
56 driver provides a unified kernel and user interface to CPU frequency
61 .Xr sysctl 8
79 configured P-state.)
87 .Bl -tag -width indent
88 .It Va dev.cpu.%d.freq
89 Current active CPU frequency in MHz.
90 .It Va dev.cpu.%d.freq_driver
93 driver used by this cpu.
94 .It Va dev.cpu.%d.freq_levels
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRTargetMachine.cpp1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
31 "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
33 /// Processes a CPU name.
34 static StringRef getCPU(StringRef CPU) { in getCPU() argument
35 if (CPU.empty() || CPU == "generic") { in getCPU()
39 return CPU; in getCPU()
47 StringRef CPU, StringRef FS, in AVRTargetMachine() argument
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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/freebsd/usr.bin/top/
H A Dtop.16 .Nd display and update information about the top cpu processes
12 .Op Fl m Ar cpu | io
26 Raw cpu percentage is used to rank the processes.
51 .Bl -tag -width indent
59 Non-printable characters in the command line are
60 encoded in C-style backslash sequences or
71 Toggle CPU display mode.
72 By default top displays the weighted CPU percentage in the WCPU column
75 displays as CPU).
79 .Dq raw cpu
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
310 /* [0x20] Specifies the state of the CPU with reference to power modes. */
463 /* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
472 /* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ
474 0 Enable the GIC CPU interface logic.
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7885.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-paren
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/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
20 cpu@0 {
21 compatible = "arm,cortex-a15";
22 device_type = "cpu";
26 cpu@1 {
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/freebsd/sys/contrib/device-tree/src/arm64/toshiba/
H A Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
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/freebsd/sys/sys/
H A Dpmc.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2008, Joseph Koshy
48 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
51 * Kernel<->userland API version number [MMmmpppp]
70 /* cpu model name for pmu lookup */
76 * We keep track of CPU variants that need to be distinguished in
77 * some way for PMC operations. CPU names are grouped by manufacturer
139 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
170 * DISABLED -- administratively prohibited from being used.
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/freebsd/sys/contrib/device-tree/Bindings/mips/
H A Dcpu_irq.txt1 MIPS CPU interrupt controller
3 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
6 With the irq_domain in place we can describe how the 8 IRQs are wired to the
13 - compatible : Should be "mti,cpu-interrupt-controller"
16 cpu-irq: cpu-irq {
17 #address-cells = <0>;
19 interrupt-controller;
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
26 compatible = "ralink,rt2880-intc";
[all …]

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